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Index > Compiler Internals > Hello and.. ADD [EAX*2], EAX

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rosasmje



Joined: 11 May 2020
Posts: 6
rosasmje
Hello from Rosasm fun :)
I was testing assembly & was wandering, if there exists ASM file with all of instructions listed in, so one can assemble and see if assembler works correctly.
Do you have such like test-file?
(also I want to add some newer instructions to rosasm, and such file will help me)

as I catch, rosasm did not care about [two-reg] position
ADD [ECX+EDX], EAX
it assembled first taped as second. so I dld your Fasm to check things;
and now I am fixing this.

01 04 11 = add [ecx][edx],eax
01 04 0A = add [edx][ecx],eax

hope this is correct

then I wrote some lines, trying as much I can, and surprisingly Fasm just skipped-missed these (crazy ones, but..):

ADD [EAX*2], EAX
ADD [ECX*2], EAX
ADD [EDX*2], EAX
ADD [EBX*2], EAX
ADD [EBP*2], EAX
ADD [ESI*2], EAX
ADD [EDI*2], EAX
Post 11 May 2020, 16:35
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 7720
Location: Kraków, Poland
Tomasz Grysztar
They are optimized for size whenever possible.
Post 11 May 2020, 16:41
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Ali.Z



Joined: 08 Jan 2018
Posts: 343
Ali.Z
rosasmje wrote:
if there exists ASM file with all of instructions listed in, so one can assemble and see if assembler works correctly.
Do you have such like test-file?
(also I want to add some newer instructions to rosasm, and such file will help me)


in my road map (for 8086 and 8086 dis/assembler) this idea will be implemented, after successfully building a normal disassembler.

as for how, you will need to make your own disassembler first. (a special build)

set a loop that will feed the disassembler with bytes, each time increment the first byte.

start with byte 00h which ADD instruction variant, append another 00h byte to it, if it assembles correctly (which it will) increase the appended byte by 1 so it becomes 00 01, and repeat upto 00 FF, then append another byte 00 00 00 which is invalid your disassembler should complain about it so then you will append another byte upto 6 bytes in protected mode (i guess)

after that increment the first byte which is the 00 (add) to becomes 01 add which is another add variant that takes different operand sizes.

and repeat for every instruction in the main opcode map, then to 2nd opcode map.

you can also do that for ISA extensions.

it would be better if at every iteration you test the bytes twice, 00 01 without prefixes and the second time with prefixes for example segment override prefix; and do not forget about address and operand size prefix as well you may also want to check if LOCK signal (a.k.a. lock prefix F0h) is valid too

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Post 11 May 2020, 16:58
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rosasmje



Joined: 11 May 2020
Posts: 6
rosasmje
[quote="Tomasz Grysztar"]They are optimized for size whenever possible.[/quote]
ah, these was assembled otherwise. sorry, i'm noob :)
and there is no option to stop optimize..
Post 11 May 2020, 17:26
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rosasmje



Joined: 11 May 2020
Posts: 6
rosasmje
Ali.Z, thank you for your suggestion, but that is too much 'other' way. and there will be aliases, which assembler will not do any ways, like 01 04 20.
it is easier to do textual copy-pastes
Post 11 May 2020, 17:30
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rosasmje



Joined: 11 May 2020
Posts: 6
rosasmje
here I collected cases, look if missed
Code:
;;;;;;;;;;short imm8 cases
ADD dword[077777777h], 033h

ADD dword[EAX], 033h
ADD dword[EAX+077h], 033h ; short displacement
ADD dword[EAX*2+077h], 033h ; will long displacement
ADD dword[EAX*4+077h], 033h
ADD dword[EAX*8+077h], 033h
; til >
ADD dword[EDI*8+077h], 033h
; except no ESP*

ADD dword[EAX+077777777h], 033h ; long displacement
ADD dword[EAX*2+077777777h], 033h
ADD dword[EAX*4+077777777h], 033h
ADD dword[EAX*8+077777777h], 033h
; til >
ADD dword[EDI*8+077777777h], 033h
; except no ESP*

ADD dword[EAX+EAX], 033h
; til >
ADD dword[EDI+EDI], 033h
; except no ESP+ESP

ADD dword[EAX+EAX*2], 033h
; til >
ADD dword[EDI+EDI*8], 033h
; except no ESP*

ADD dword[EAX+EAX+077h], 033h ; short displacement
; til >
ADD dword[EDI+EDI+077h], 033h
; except no ESP+ESP
; ESP always BASE (left)

ADD dword[EAX+EAX*2+077h], 033h
; til >
ADD dword[EDI+EDI*4+077h], 033h
; except no ESP*
; ESP always BASE (left)

ADD dword[EAX+EAX*8+077h], 033h
; til >
ADD dword[EDI+EDI*8+077h], 033h
; except no ESP*
; ESP always BASE (left)

ADD dword[EAX+EAX+077777777h], 033h ; long displacement
; til >
ADD dword[EDI+EDI*8+077777777h], 033h
; no ESP*
; ESP always BASE (left)



;;;;;;;;;;;long imm32
ADD dword[077777777h], 033333333h

ADD dword[EAX], 033333333h
; til >
ADD dword[EDI], 033333333h

ADD dword[EAX+077h], 033333333h ; short displacement
ADD dword[EAX*2+077h], 033333333h ; will long displacement
ADD dword[EAX*4+077h], 033333333h
ADD dword[EAX*8+077h], 033333333h
; til >
ADD dword[EDI*8+077h], 033333333h
; except no ESP*

ADD dword[EAX+EAX+077h], 033333333h ; short displacement
; til >
ADD dword[EDI+EDI*8+077h], 033333333h
; no ESP+ESP, no ESP*
; ESP always BASE (left)

ADD dword[EAX+077777777h], 033333333h ; long displacement
ADD dword[EAX*2+077777777h], 033333333h
ADD dword[EAX*4+077777777h], 033333333h
ADD dword[EAX*8+077777777h], 033333333h
; til >
ADD dword[EDI*8+077777777h], 033333333h
; except no ESP*


ADD dword[EAX+EAX], 033333333h
; no ESP+ESP
ADD dword[EDI+EDI], 033333333h
; ESP always BASE (left)

ADD dword[EAX+EAX*2], 033333333h
; til >
ADD dword[EDI+EDI*8], 033333333h
; no ESP+ESP, no ESP*
; ESP always BASE (left)

ADD dword[EAX+EAX+077777777h], 033333333h
; til >
ADD dword[EDI+EDI*8+077777777h], 033333333h
; no ESP+ESP, no ESP*
; ESP always BASE (left)




;;;;;;;;;;;;second OP reg
ADD dword[EAX], EAX
; til >
ADD dword[EDI], EDI


ADD dword[EAX+077h], EAX ; short displacement
; til >
ADD dword[EDI+077h], EDI



ADD dword[EAX+077777777h], EAX ; long displacement
; til >
ADD dword[EDI+077777777h], EAX


ADD dword[EAX*2], EAX
; til >
ADD dword[EDI*8], EDI
; no ESP*

ADD dword[EAX*2+077h], EAX ; will long displacement
; til >
ADD dword[EDI*8+077h], EDI
; no ESP*

ADD dword[EAX*2+077777777h], EAX ; long displacement
; til >
ADD dword[EDI*8+077777777h], EAX
; no ESP*

ADD dword[EAX+EAX], EAX
; til >
ADD dword[EDI+EDI], EAX
; no ESP+ESP

ADD dword[EAX+EAX*2], EAX
; til >
ADD dword[EDI+EDI*8], EAX
; no ESP*

ADD dword[EAX+EAX+077h], EAX ; short displacement
; til >
ADD dword[EDI+EDI+077h], EAX
; no ESP+ESP

ADD dword[EAX+EAX*2+077h], EAX
; til >
ADD dword[EDI+EDI*8+077h], EAX
; no ESP*


ADD dword[EAX+EAX+077777777h], EAX ; long displacement
; til >
ADD dword[EDI+EDI+077777777h], EAX
; no ESP+ESP

ADD dword[EAX+EAX*2+077777777h], EAX
; til >
ADD dword[EDI+EDI*8+077777777h], EAX
; no ESP*
    
Post 12 May 2020, 19:22
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Ali.Z



Joined: 08 Jan 2018
Posts: 343
Ali.Z
i did not check if you missed anything, but i noticed one mistake:

Code:
;;;;;;;;;;short imm8 cases
ADD dword[077777777h], 033h ; this is not imm8
; because you specified the size as dword so it should be assembled as 00000033h the assembler would zero-extend the 33

;;;;;;;;;;;long imm32
ADD dword[077777777h], 033333333h ; this is imm32    


so you better do size checking, and count BYTE, WORD, DWORD and QWORD (QWORD in long mode).

it would take countless months if you want to write every possible instruction, so you should handle this to computers.

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Post 12 May 2020, 20:03
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rosasmje



Joined: 11 May 2020
Posts: 6
rosasmje
no, I am correct. ADD instruction has imm8 version.
ADD dword[077777777h], 033h in byte code is 83 05 77 77 77 77 33.
(thar is why choose ADD, not MOV)
I asked, if I am missing some cases. (byte word ignore)
Post 12 May 2020, 20:52
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Ali.Z



Joined: 08 Jan 2018
Posts: 343
Ali.Z
Ali.Z wrote:
it should be assembled as 00000033h the assembler would zero-extend the 33


i apologize, i checked the manual and that is indeed valid.
its in fact sign-extended by the CPU but not by the assembler.

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Asm For Wise Humans
Post 12 May 2020, 21:16
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rosasmje



Joined: 11 May 2020
Posts: 6
rosasmje
rearranged list. now all it needs is search-replace function for other functions/small_regs/B,W,D sizes.

Code:
;;;;;;;;;; OP2 short imm8 cases
ADD dword[077777777h], 033h

ADD dword[EAX], 033h
; til EDI

ADD dword[EAX+077h], 033h ; short displacement
; til EDI

ADD dword[EAX+077777777h], 033h ; long displacement
ADD dword[EAX*2+077777777h], 033h
ADD dword[EAX*4+077777777h], 033h
ADD dword[EAX*8+077777777h], 033h
; til > EDI

ADD dword[EAX+EAX], 033h
ADD dword[EAX+EAX*2], 033h
ADD dword[EAX+EAX*4], 033h
ADD dword[EAX+EAX*8], 033h
; til > EDIs

ADD dword[EAX+EAX+077h], 033h ; short displacement
ADD dword[EAX+EAX*2+077h], 033h
ADD dword[EAX+EAX*4+077h], 033h
ADD dword[EAX+EAX*8+077h], 033h
; til > EDIs

ADD dword[EAX+EAX+077777777h], 033h ; long displacement
ADD dword[EAX+EAX*2+077777777h], 033h
ADD dword[EAX+EAX*4+077777777h], 033h
ADD dword[EAX+EAX*8+077777777h], 033h
; til > EDIs


;;;;;;;;;;; OP2 long imm32
ADD dword[077777777h], 033333333h

ADD dword[EAX], 033333333h
; til EDI

ADD dword[EAX+077h], 033333333h ; short displacement
; til EDI

ADD dword[EAX+077777777h], 033333333h ; long displacement
ADD dword[EAX*2+077777777h], 033333333h
ADD dword[EAX*4+077777777h], 033333333h
ADD dword[EAX*8+077777777h], 033333333h
; til > EDI

ADD dword[EAX+EAX], 033333333h
ADD dword[EAX+EAX*2], 033333333h
ADD dword[EAX+EAX*4], 033333333h
ADD dword[EAX+EAX*8], 033333333h
; til > EDIs

ADD dword[EAX+EAX+077h], 033333333h ; short displacement
ADD dword[EAX+EAX*2+077h], 033333333h
ADD dword[EAX+EAX*4+077h], 033333333h
ADD dword[EAX+EAX*8+077h], 033333333h
; til > EDIs

ADD dword[EAX+EAX+077777777h], 033333333h ; long displacement
ADD dword[EAX+EAX*2+077777777h], 033333333h
ADD dword[EAX+EAX*4+077777777h], 033333333h
ADD dword[EAX+EAX*8+077777777h], 033333333h
; til > EDIs


;;;;;;;;;;;;second OP reg
ADD dword[077777777h], EAX

ADD dword[EAX], EAX
; til > EDIs

ADD dword[EAX+077h], EAX ; short displacement
; til > EDI

ADD dword[EAX+077777777h], EAX ; long displacement
ADD dword[EAX*2+077777777h], EAX
ADD dword[EAX*8+077777777h], EAX
ADD dword[EAX*8+077777777h], EAX
; til > EDI

ADD dword[EAX+EAX], EAX
ADD dword[EAX+EAX*2], EAX
ADD dword[EAX+EAX*4], EAX
ADD dword[EAX+EAX*8], EAX
; til > EDis

ADD dword[EAX+EAX+077h], EAX ; short displacement
ADD dword[EAX+EAX*2+077h], EAX
ADD dword[EAX+EAX*4+077h], EAX
ADD dword[EAX+EAX*8+077h], EAX
; til > EDIs

ADD dword[EAX+EAX+077777777h], EAX ; long displacement
ADD dword[EAX+EAX*2+077777777h], EAX
ADD dword[EAX+EAX*4+077777777h], EAX
ADD dword[EAX+EAX*8+077777777h], EAX
; til > EDIs

;;;;;;;;;excepts
; ESP always BASE (left)
; no ESP+ESP
; no ESP*
    
[/code]
Post 13 May 2020, 16:52
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