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flat assembler > Examples and Tutorials > Intel® 64 Architecture Processor Topology Enumeration

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yeohhs



Joined: 19 Jan 2004
Posts: 170
Location: N 5.43564° E 100.3091°
An interesting article (with source codes) from Intel.
https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration

Quote:

Processor topology information is important for a number of processor-resource management practices, ranging from task/thread scheduling, licensing policy enforcement, affinity control/migration, etc. Topology information of the cache hierarchy can be important to optimizing software performance. This white paper covers topology enumeration algorithm for single-socket to multiple-socket platforms using Intel 64 and IA-32 processors. The topology enumeration algorithms (both processor and cache) using initial APIC ID has been extended to use x2APIC ID, the latter mechanism is required for future platforms supporting more than 256 logical processors in a coherent domain.

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Post 29 Jan 2018, 05:40
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