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Tomasz Grysztar 27 Oct 2015, 12:03
CandyMan wrote:
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27 Oct 2015, 12:03 |
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CandyMan 27 Oct 2015, 13:10
Code: use16 vpgatherdd xmm0{k1},[rax+xmm0+64] Code: check_vsib: xor ah,ah check_vsib_base: ;* test bh,bh jz check_vsib_index mov al,bh shr al,4 cmp al,4 je check_vsib_base_size cmp [code_type],64 jne swap_vsib_registers ;* cmp al,8 jne swap_vsib_registers check_vsib_base_size: mov ah,[address_size] and ah,0Fh jz check_vsib_index cmp al,ah jne invalid_address check_vsib_index: mov al,bl and al,0E0h cmp al,0C0h jae check_index_scale cmp al,60h je check_index_scale jmp invalid_address swap_vsib_registers: xor al,-1 jz invalid_address cmp cl,1 ja invalid_address xchg bl,bh mov cl,1 jmp check_vsib_base ;* closed loop _________________ smaller is better |
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27 Oct 2015, 13:10 |
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Tomasz Grysztar 27 Oct 2015, 13:13
No, I meant the second one of your samples. The first one is already fixed.
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27 Oct 2015, 13:13 |
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CandyMan 27 Oct 2015, 13:46
Whether you could what combinations of registers are disallowed?
thanks... _________________ smaller is better |
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27 Oct 2015, 13:46 |
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Tomasz Grysztar 27 Oct 2015, 14:12
The disallowed combinations are defined in Intel manuals this way:
Intel wrote: The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. Code: vpgatherdd xmm0{k1},dword [eax+xmm0+0x40] ; error: disallowed combination of registers |
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27 Oct 2015, 14:12 |
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