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flat assembler > Windows > PiD(Processor Identifier)

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Asm++



Joined: 04 Feb 2013
Posts: 24
Location: On a Chip!
Hi everybody,
This is a simple and small Windows application that I have written completely in assembly using FASM, and I'd like to share it with you in a hope to be useful, its job is to retrieve processor information.
Now it's able to identify about 66 features.
I hope you find it useful.

Best regards. Very Happy


Description: PiD(Processor Identifier)
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Filename: PiD.zip
Filesize: 10.36 KB
Downloaded: 100 Time(s)


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Post 30 Apr 2013, 23:05
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typedef



Joined: 25 Jul 2010
Posts: 2910
Location: 0x77760000
Anything else we need to know before we double-click on this exe.

Source code?
Post 01 May 2013, 00:54
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nmaps



Joined: 26 Oct 2012
Posts: 8
Due to the license agreement, I am unable to debug your application and thus cannot run it. Luckily, I can examine files on my hard drive without agreeing to your license, so popping it open in IDA revealed that it appears to be trustworthy. Although that first data section is awfully large and full of unitialized 0xff's. Heap memory plz?

Quote:
B- Restrictions:
1- You are NOT allowed to Analyze, Modify, Decompile, Disassemble, Reverse Engineering and/or Debug this software and/or any part of it.
Post 31 May 2013, 04:12
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tthsqe



Joined: 20 May 2009
Posts: 720
This is a nice little program, but it reeks of hubris.
My processor is intel i7 - 2600K CPU, which I know to have 4 core, 8 threads.
This program reports correctly from cpuid that the "Core Count" is 8 and the "Thread Count" is 16, and I believe it. Are these extra cores (and threads from hyper-threading) simply disabled to increase yield?
Post 31 May 2013, 06:23
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16125
Location: Hyperborea
tthsqe wrote:
Are these extra cores (and threads from hyper-threading) simply disabled to increase yield?
Yes and no. For your CPU that answer is no. You will have 8+8 fully functioning cores. For other, cheaper, CPUs the answer might be yes depending upon which CPU the user has. If cores are disabled then you can't use them and the returned metrics from CPUID won't show them.
Post 31 May 2013, 07:06
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tthsqe



Joined: 20 May 2009
Posts: 720
I simply can't believe that I have a 16 core processor. It was marketed as a quad core, behaves like a quad core with HT, and show 8 threads to OS.
A search of the intel docs turned up the information
Code:
CPUID.1.EBX[23:16]:
Maximum number of logical processors per package
(or can also be considered the number of APIC IDs reserved for this package)
This value does not change when processor cores are disabled by software.
CPUID.4.EAX[31:26]+1:
Maximum number of processor cores in this physical package.
This value does not change when cores are disabled by software    

So it seems that cpuid is returning the maximum capacity of the die, indicating that my CPU was cut from the same kind of wafers that house the really big 8 core 16 thread server processors.
Asm++, i would suggest that you use some OS functions to determine a less misleading core and thread count. Otherwise your users (or customers?) will likely be just as confused as I am.
Post 31 May 2013, 08:08
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16125
Location: Hyperborea
Sorry I erred above, I meant to say 4+4 cores. Somehow I added 4 and 4 together too many times.
Post 31 May 2013, 08:58
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bitRAKE



Joined: 21 Jul 2003
Posts: 2667
Location: dank orb
What's this "Multi-NOP"?

If I can do more NOPs then I want to figure out how. Wink
Post 01 Jun 2013, 01:15
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alessandro95



Joined: 24 Mar 2013
Posts: 62
I'm not sure if this is what the author of the program meant but some CPUs (I think sandy bridge or newer all support this) can deal with NOPs (also multi-byte ones) without having to use any execution unit so that they can do 4 NOPs per clock cycle
Post 01 Jun 2013, 07:30
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16125
Location: Hyperborea
alessandro95 wrote:
... some CPUs (I think sandy bridge or newer all support this) can deal with NOPs (also multi-byte ones) without having to use any execution unit so that they can do 4 NOPs per clock cycle
This is something that has always baffled me. CPU makers seem to delight in boasting about how fantastic their CPU is at doing nothing. Whereas, when I write a program I much prefer to keep my CPU doing something useful. Sure there is a very small usage case for multiple nops to do loop entry alignment but it is hardly a significant portion of runtime for any useful code (i.e. not just a specially designed test case).
Post 01 Jun 2013, 08:18
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alessandro95



Joined: 24 Mar 2013
Posts: 62
you have a point there Very Happy
anyway on the sandy bridge CPUs (I guess also on newer ones, would make sense) also XOR, SUB, PXOR, XORPS, XORPD, VXORPS and VXORPD are treated the same way as NOPs when the 2 parameters are the same register, which looks more useful
Post 01 Jun 2013, 09:03
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bitRAKE



Joined: 21 Jul 2003
Posts: 2667
Location: dank orb
Well, my Harpertowns have it, so I went looking because I never heard of it before. And I still remain in the dark about it. I am very intrigued to hear the author's response. SIV doesn't seem to display a similar named flag. Yet, there is an unknown bit listed and active.

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Post 01 Jun 2013, 10:54
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