x64 is not truly a 64bit procesor

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revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20335
Location: In your JS exploiting you and your system

revolution 17 Sep 2012, 00:26

JohnFound wrote:

Well, my definition: The bit-ness of the CPU is equal to the maximal bit-ness of the source data for "and" instruction. (available on all known CPUs).

So you are also choosing the ALU width. I agree.

17 Sep 2012, 00:26

Feryno

Joined: 23 Mar 2005
Posts: 509
Location: Czech republic, Slovak republic

Feryno 17 Sep 2012, 08:33

nop wrote:

x64 is not truly a 64bit procesor

yes and I'm guessing the feature expansion for full 64 bit will be here:
EFER.LMA=1, CS.L=1, CS.D=1
currently the D bit must be 0 (partial 64 bit mode mixed with 32 bits old age
heritage)

from manuals:

Quote:

If CS.L = 1 and IA-32e mode is active, the only valid setting is CS.D = 0. This setting indicates a default
operand size of 32 bits and a default address size of 64 bits. The CS.L = 1 and CS.D = 1 bit combination is
reserved for future use and a #GP fault will be generated on an attempt to use a code segment with these
bits set in IA-32e mode

17 Sep 2012, 08:33

nop

Joined: 01 Sep 2008
Posts: 165
Location: right here left there

nop 17 Sep 2012, 15:40

i did not start this silly tread Evil or Very Mad

some mod did it for fun Evil or Very Mad

i suspect revolution and he cut out this coment

revolution wrote:

The x86 encoding mechanism for immediate values only allows 32-bit signed values with ADD in 64-bit mode.

he knows the true answer but he just likes to argue Razz

17 Sep 2012, 15:40

revolution
When all else fails, read the source

Joined: 24 Aug 2004
Posts: 20335
Location: In your JS exploiting you and your system

revolution 17 Sep 2012, 15:51

nop wrote:

i did not start this silly tread some mod did it for fun i suspect revolution and he cut out this coment
revolution wrote:
The x86 encoding mechanism for immediate values only allows 32-bit signed values with ADD in 64-bit mode.
he knows the true answer but he ...

It might have been me but the 'he' thing confused me. Are you sure I am a 'he'?

nop wrote:

... just likes to argue

No I don't Wink

17 Sep 2012, 15:51

cod3b453

Joined: 25 Aug 2004
Posts: 618

cod3b453 17 Sep 2012, 17:35

I would say the size of the GPRs; ALUs are obviously tied to this but the likes of carry/upper and lower product/remainder don't exist in every architecture.

17 Sep 2012, 17:35

nop

Joined: 01 Sep 2008
Posts: 165
Location: right here left there

nop 19 Sep 2012, 16:24

the starter of this silly thred who also invented the silly title shud define what he or she or it means by the silly term bit-ness Razz

19 Sep 2012, 16:24

nop

Joined: 01 Sep 2008
Posts: 165
Location: right here left there

nop 04 Oct 2012, 16:56

revolution wrote:

nop wrote:
i did not start this silly tread some mod did it for fun i suspect revolution and he cut out this coment
revolution wrote:
The x86 encoding mechanism for immediate values only allows 32-bit signed values with ADD in 64-bit mode.

It might have been me

@revolution i am still waiting for you to please fix this thread with its silly title that you started but you made it look like it was me and it makes me angry Evil or Very Mad

04 Oct 2012, 16:56

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