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Index > Compiler Internals > bugs & instruction missing (1.69.47)

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CandyMan



Joined: 04 Sep 2009
Posts: 319
Location: film "CandyMan" directed through Bernard Rose OR Candy Shop
CandyMan
BEXTR r8,r9,12345678h equal? BEXTR r8d,r9d,12345678h
VCVTDQ2PD ymm8,[rax] equal? VCVTDQ2PD xmm8,[rax]
VCVTPS2PD ymm8,[rax] equal? VCVTPS2PD xmm8,[rax]

next bug in:

LWPINS reg32.vvvv, reg/mem32, imm32 8F RXB.0A 0.src1.0.00 12 /0 /imm32
LWPINS reg64.vvvv, reg/mem32, imm32 8F RXB.0A 1.src1.0.00 12 /0 /imm32
LWPVAL reg32.vvvv, reg/mem32, imm32 8F RXB.0A 0.src1.0.00 12 /1 /imm32
LWPVAL reg64.vvvv, reg/mem32, imm32 8F RXB.0A 1.src1.0.00 12 /1 /imm32

missing instructions:

VEX.128.66.0F38.W0 18 /r VBROADCASTSS xmm1,xmm2
VEX.256.66.0F38.W0 18 /r VBROADCASTSS ymm1,xmm2
VEX.256.66.0F38.W0 19 /r VBROADCASTSD ymm1,xmm2

VEX.NDS.128.66.0F3A.W0 02 /r ib VPBLENDD xmm1,xmm2,xmm3/m128,imm8
VEX.NDS.256.66.0F3A.W0 02 /r ib VPBLENDD ymm1,ymm2,ymm3/m256,imm8

VEX.128.66.0F38.W0 78 /r VPBROADCASTB xmm1,xmm2/m8
VEX.256.66.0F38.W0 78 /r VPBROADCASTB ymm1,xmm2/m8
VEX.128.66.0F38.W0 79 /r VPBROADCASTW xmm1,xmm2/m16
VEX.256.66.0F38.W0 79 /r VPBROADCASTW ymm1,xmm2/m16
VEX.128.66.0F38.W0 58 /r VPBROADCASTD xmm1,xmm2/m32
VEX.256.66.0F38.W0 58 /r VPBROADCASTD ymm1,xmm2/m32
VEX.128.66.0F38.W0 59 /r VPBROADCASTQ xmm1,xmm2/m64
VEX.256.66.0F38.W0 59 /r VPBROADCASTQ ymm1,xmm2/m64

VEX.NDS.128.66.0F38.W0 8C /r VPMASKMOVD xmm1,xmm2,m128
VEX.NDS.256.66.0F38.W0 8C /r VPMASKMOVD ymm1,ymm2,m256
VEX.NDS.128.66.0F38.W1 8C /r VPMASKMOVQ xmm1,xmm2,m128
VEX.NDS.256.66.0F38.W1 8C /r VPMASKMOVQ ymm1,ymm2,m256
VEX.NDS.128.66.0F38.W0 8E /r VPMASKMOVD m128,xmm1,xmm2
VEX.NDS.256.66.0F38.W0 8E /r VPMASKMOVD m256,ymm1,ymm2
VEX.NDS.128.66.0F38.W1 8E /r VPMASKMOVQ m128,xmm1,xmm2
VEX.NDS.256.66.0F38.W1 8E /r VPMASKMOVQ m256,ymm1,ymm2

VEX.256.66.0F38.W0 5A /r VBROADCASTI128 ymm1,m128

VCVTPH2PS xmm1,xmm2/mem64,imm8 8F RXB.08 0.1111.0.00 A0 /r imm8
VCVTPH2PS ymm1,xmm2/mem128,imm8 8F RXB.08 0.1111.1.00 A0 /r imm8
Post 22 Mar 2012, 00:49
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7796
Location: Kraków, Poland
Tomasz Grysztar
Thank you for the report.
I have applied the corrections, except for immediate form of VCVTPH2PS, because I could not find it in the latest AMD manuals. Can you point me to the document that contains it?
Post 22 Mar 2012, 10:31
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madmatt



Joined: 07 Oct 2003
Posts: 1045
Location: Michigan, USA
madmatt
You can find them in the new intel manuals. In case you don't like downloading individual manuals, Intel has come out with an all-in-one manual (~32mb file).
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
Post 22 Mar 2012, 15:34
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Tomasz Grysztar



Joined: 16 Jun 2003
Posts: 7796
Location: Kraków, Poland
Tomasz Grysztar
Not these, the forms defined by Intel are the two-operand forms (without the immediate), which are part of F16C and are supported by fasm since 1.69.15.
And you can see that the encoding for immediate forms mentioned by CandyMan uses XOP prefix, so it cannot be Intel, it must be AMD.
Post 22 Mar 2012, 15:48
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CandyMan



Joined: 04 Sep 2009
Posts: 319
Location: film "CandyMan" directed through Bernard Rose OR Candy Shop
CandyMan
immediate form of VCVTPH2PS I found in old nasm documentation but now it is removed
Post 22 Mar 2012, 17:09
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madmatt



Joined: 07 Oct 2003
Posts: 1045
Location: Michigan, USA
madmatt
Tomasz Grysztar wrote:
Not these, the forms defined by Intel are the two-operand forms (without the immediate), which are part of F16C and are supported by fasm since 1.69.15.
And you can see that the encoding for immediate forms mentioned by CandyMan uses XOP prefix, so it cannot be Intel, it must be AMD.


Yeh, ok, did some googling and this is the only place I've found so far that has the 3-byte instruction format:
http://www.sandpile.org/x86/opc_3.htm

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Post 23 Mar 2012, 14:42
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