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> Main > where is the "base address" of PIIX3 ? |
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ouadji 13 Apr 2011, 22:08
from INTEL "290566-001.pdf" (IOAPIC - 82093AA) clic .... Memory Mapped Registers For Accessing IOAPIC Registers = FEC0xy00h "xy" are determined by the x and y fields in the "APIC Base Address Relocation Register" ... this register is located in the PIIX3. (Range for x = 0-Fh and the range for y = 0,4,8,Ch) from INTEL "290550-002.pdf" (PIIX3 - 82371SB) clic ... APIC BASE ADDRESS RELOCATION REGISTER (Function 0) (PIIX3) Address Offset: 80h Default Value: 00h Attribute: Read/Write This register provides the modifier for the APIC base address. APIC is mapped in the memory space at the locations FEC0_xy00h and FEC0_xy10h (x=0-Fh, y=0,4,8,Ch). The value of ’y’ is defined by bits [1,0] and the value of ’x’ is defined by bits [5:2]. where is the "base address" of PIIX3 ??? (I think that's the south bridge controller) thank you all, [/url] |
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13 Apr 2011, 22:08 |
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ouadji 14 Apr 2011, 08:13
thank you very much Alphonso |
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14 Apr 2011, 08:13 |
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edfed 14 Apr 2011, 09:48
where is the uptodate port list of the PC? for example, port list of a recent laptop with a recent CPU?
because everywhere i look, the port list is a little outdated, like 10 years old, or more. it can be interresting too to have a port list of every major pci, isa, agp, etc cards. even if these datas maybe proprietary, it can be very good to know them. there are not so much pci cards models. |
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14 Apr 2011, 09:48 |
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neville 14 Apr 2011, 20:16
edfed wrote: it can be interresting too to have a port list of every major pci, isa, agp, etc cards... there are not so much pci cards models. But I totally agree with your sentiments edfed. The pity is that more and more of our beloved pc's are being built with proprietary bits which is taking a lot of the fun out of them _________________ FAMOS - the first memory operating system |
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14 Apr 2011, 20:16 |
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ouadji 14 Apr 2011, 22:02
i found de solution IOAPIC Base address = 0xFECxy000 but what are the values of : "xy" ICH10 controller... Code: ;319973.pdf (Intel® I/O Controller Hub 10 ICH10 Family) ;(1) ;RCBA Root Complex Base Address Register ---> 319973.pdf/13.1.36 ;bus:0 device:31 function:0 Offset:F0-F3h (R/W 32 bits) ;[31:14] Base Address (BA) for the root complex register block decode range. ; aligned on a 16-KB boundary - R/W ;[13:1] Reserved ;[0] Enable (EN) — R/W. When set, enables the range specified in BA to be claimed as the ; Root Complex Register Block. ;(2) ;After that : 319973.pdf/10.1.68 (APIC Range Select - ASEL) ;Offset Address: 31FE–31FFh 16bits r/w mov eax,0x8000F8F0 ;bus:0 device:31 function:0 Offset:F0 mov dx,0cf8h ; thank to Alphonso out dx,eax mov dx,0cfch in eax,dx and eax,not 0x3FFF ;physical RCBA invoke MmMapIoSpace, eax, 0, 4*PAGE_SIZE, mNonCached push eax ;eax = mapped RCBA mov bx,[eax + 0x31FE] ;bl == xy <<========== here ;Default Value: 00h -> 0xFEC(00)000 pop eax invoke MmUnmapIoSpace, eax, 4*PAGE_SIZE |
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14 Apr 2011, 22:02 |
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