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b1528932



Joined: 21 May 2010
Posts: 287
b1528932
- how do i detect if cpu is able to enter protected mode?
- how can i determine that 0x66 and 0x67 prefix is allowed (real mode)?


if its on manual, im sorry but i cant find it. tell me what chapter.
Post 22 Jun 2010, 09:47
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17716
Location: In your JS exploiting you and your system
revolution
Read:

Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 3A:
System Programming Guide, Part 1

CHAPTER 18
ARCHITECTURE COMPATIBILITY
Post 22 Jun 2010, 10:00
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ouadji



Joined: 24 Dec 2008
Posts: 1081
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ouadji

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Post 22 Jun 2010, 10:34
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b1528932



Joined: 21 May 2010
Posts: 287
b1528932
no information about 0x66 prefix.

how do i know if i can use it?
Post 22 Jun 2010, 11:24
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ouadji



Joined: 24 Dec 2008
Posts: 1081
Location: Belgium
ouadji
Intel® 64 and IA-32 Architectures Optimization Reference Manual
3.4.2.3 Length-Changing Prefixes (LCP)


The length of an instruction can be up to 15 bytes in length. Some prefixes can
dynamically change the length of an instruction that the decoder must recognize.
Typically, the pre-decode unit will estimate the length of an instruction in the byte
stream assuming the absence of LCP. When the predecoder encounters an LCP in the
fetch line, it must use a slower length decoding algorithm. With the slower length
decoding algorithm, the predecoder decodes the fetch in 6 cycles, instead of the
usual 1 cycle. Normal queuing throughout of the machine pipeline generally cannot
hide LCP penalties.
The prefixes that can dynamically change the length of a instruction include:
• operand size prefix (0x66)
• address size prefix (0x67)

http://www.intel.com/Assets/PDF/manual/248966.pdf

also : 2.1.2.2 Instruction Fetch Unit / Instruction PreDecode

all processors based on x86 architecture are be able to do that.
all cpu based on x86 architecture are be able to enter protected mode too ...
(all cpu since 80286)


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Post 22 Jun 2010, 11:38
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b1528932



Joined: 21 May 2010
Posts: 287
b1528932
Quote:
all processors based on x86 architecture are be able to do that.


so when i start executing my bootloader the first thing i should do is testing for cpuid in eflags.id?

can i assume that i have access to upper 16 bits of eflags, and consequently being 32bit address aware?
Post 22 Jun 2010, 21:22
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baldr



Joined: 19 Mar 2008
Posts: 1651
baldr
b1528932,

Probably you can safely assume 386+ CPU, or check and say "Upgrade your box, or press any key if you're brave enough."

cpuid is Pentium+/later 486 feature.
Post 22 Jun 2010, 21:52
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bitshifter



Joined: 04 Dec 2007
Posts: 764
Location: Massachusetts, USA
bitshifter
This was in the old Wofenstein3D sources Razz
Code:
PROC    _CheckIs386
PUBLIC  _CheckIs386

        pushf                   ; Save flag registers, we use them here
        xor     ax,ax           ; Clear AX and...
        push ax                 ; ...push it onto the stack
        popf                    ; Pop 0 into flag registers (all bits to 0),
        pushf                   ; attempting to set bits 12-15 of flags to 0's
        pop     ax                      ; Recover the save flags
        and     ax,08000h       ; If bits 12-15 of flags are set to
        cmp     ax,08000h       ; zero then it's 8088/86 or 80188/186
        jz      not386

        mov     ax,07000h       ; Try to set flag bits 12-14 to 1's
        push ax                 ; Push the test value onto the stack
        popf                    ; Pop it into the flag register
        pushf                   ; Push it back onto the stack
        pop     ax                      ; Pop it into AX for check
        and     ax,07000h       ; if bits 12-14 are cleared then
        jz      not386          ; the chip is an 80286

        mov     ax,1            ; We now assume it's a 80386 or better
        popf
        retf

not386:
        xor     ax,ax
        popf
        retf

        ENDP    
    

Its in TASM IDEAL syntax!
Post 23 Jun 2010, 04:01
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Tyler



Joined: 19 Nov 2009
Posts: 1216
Location: NC, USA
Tyler
HelpPC, Misc -> CPU topic wrote:

8088,80188,V20 six byte prefetch queue, allows use of self

modifying code to determine length of prefetch



8086,80186,V30 four byte prefetch queue, allows use of self

modifying code to determine length of prefetch



8088,8086,80188,81086,v20,v30 Flag register bits 12 through

15 cannot be cleared



8088,8086 will shift left or right using all 8 bits of

CL, if CL = 33, register is guaranteed to be

cleared



80188,80186,80286,80386 will shift left or right using only

lower 5 bits of CL. If CL = 32, the shift will

not occur



80286,80386 earlier CPU's decremented SP before a PUSH SP, but

286+ pushes the value first then, decrements SP



8088,8086 non-zero multiplication result clears zero flag



V20,V30 non-zero multiplication result does not clear

zero flag, set ZF before multiply, and test after,

if it's still set, then it's a V20, V30



80286 allows setting of bit 15 of the flags register



80386 allows setting of bits 12 through 14 of flags register

Post 11 Jul 2010, 01:06
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