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dosin



Joined: 24 Aug 2007
Posts: 337
dosin
Thanks - That was very helpful! Very Happy
Post 13 Jan 2010, 02:29
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dosin



Joined: 24 Aug 2007
Posts: 337
dosin
this is the example I been looking at:
http://wiki.osdev.org/Setting_Up_Paging

So far nothing seams to be working.. any ideas?


Code:
removed - bad code  :oops: 
    


or is there something wrong or do I need to set up something else before this.. ???


Last edited by dosin on 16 Jan 2010, 23:15; edited 2 times in total
Post 16 Jan 2010, 16:08
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egos



Joined: 10 Feb 2009
Posts: 144
egos
It's crazy assembly code because you made very bad translation. Here is code for setting identity mapping for first 4 mb of RAM and recursive page dir mapping.
Code:
PF_PRESENT equ 1
PF_WRITABLE equ 2
PF_APL equ 4

PAGE_LOCAL equ (PF_PRESENT+PF_WRITABLE+PF_APL)

  ...

; df = 0, es = data sel

  call .GetPage ; page dir
  mov ebx,eax

  call .GetPage ; 1st page tab (it is temporary)
  mov edi,eax
  mov ecx,1024
  mov eax,PAGE_LOCAL
@@:
  stosd
  add eax,1000h
  loop @b

  lea eax,[edi-1000h+PAGE_LOCAL]
  mov edi,ebx
  stosd
  mov ecx,1022
  xor eax,eax
  rep stosd
  lea eax,[ebx+PAGE_LOCAL-PF_APL]
  stosd

  mov cr3,ebx
  mov eax,cr0
  or eax,80000000h
  mov cr0,eax

  ...    
Post 16 Jan 2010, 19:16
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dosin



Joined: 24 Aug 2007
Posts: 337
dosin
Quote:
It's crazy assembly code because you made very bad translation.


I can see that.. Thank you- for helping!
Post 16 Jan 2010, 21:07
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dosin



Joined: 24 Aug 2007
Posts: 337
dosin
off subject question:

in Pmode - is there a way to get the full amount of system memory avail?
Post 18 Jan 2010, 21:56
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edfed



Joined: 20 Feb 2006
Posts: 4242
Location: 2018
edfed
yep.
with paging.


i explain, the first thing to do with paging is:

set a page to memory linear 0
access memory 0 in the page
increment linear.
access memory 0 in the page
etc etc

when there is a page fault, it means there is no page at this place.

i think increment of 4MBytes can be good, then, a 4MB page is needed.
but you can also make a 4KB page.


don't forget to set a bitmap during memory test.

this test can be done with no paging, with a direct access to memory.
but now, you will read it, wrtie it, read it, restore it
read it
and maybe some cases will be problematic.

correction: 2MB = 4MB, 2MB is irrelevant in IA32 mode.


Last edited by edfed on 22 Jan 2010, 11:20; edited 1 time in total
Post 18 Jan 2010, 22:07
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dosin



Joined: 24 Aug 2007
Posts: 337
dosin
I think I am getting closer.. but still crashing..
is there something that needs to be done after I load the cr0?
or am I still wrong on making the table and page entries?

Code:
;Set page dir: all to 0x00000007
xor eax,eax
xor edi,edi
xor ecx,ecx
       
mov edi,0x9C000
mov ecx,1024 
or eax,7 
@@: stosd 
loop @b 

;load 1st table 

xor eax,eax
mov edi,0x9D000
mov ecx,1024 
@@: 
or  eax,7
stosd
add eax,4096
loop @b 

;fill 2st table
mov edi,0x9E000
mov ecx,1024 
@@: 
or  eax,7
stosd
add eax,4096
loop @b 
    
;fill 3rd table
mov edi,0x9F000
mov ecx,1024 
@@: 
or  eax,7
stosd
add eax,4096
loop @b               
    
;load pages into dir
mov edi,0x9C000
mov dword[edi+0*4],0x9D000
or  dword[edi+0*4],7
   
mov dword[edi+1*4],0x9E000
or  dword[edi+1*4],7
      
mov dword[edi+2*4],0x9F000
or  dword[edi+2*4],7
      
mov eax,0x9C000
mov cr3,eax

      
mov   eax,cr0
or    eax,0x80000000       
mov   cr0,eax
    


I am running in qemu....
This is the reg dump from qemu
Code:
qemu: fatal: Trying to execute code outside RAM or ROM at 0x0000081f

EAX=e0000011 EBX=00001340 ECX=00000000 EDX=000003f2
ESI=ffff0fff EDI=0009c000 EBP=000007f8 ESP=00001000
EIP=000001ff EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0008 00000000 ffffffff 00cff300
CS =0010 00000620 ffffffff 00cf9a00
SS =0018 00000620 ffffffff 00cf9300
DS =0018 00000620 ffffffff 00cf9300
FS =0018 00000620 ffffffff 00cf9300
GS =0008 00000000 ffffffff 00cff300
LDT=0000 00000000 0000ffff 00008000
TR =0000 00000000 0000ffff 00008000
GDT=     000012d8 00000067
IDT=     00001340 000007ff
CR0=e0000011 CR2=00000000 CR3=0009c000 CR4=00000000
CCS=00001000 CCD=e0000011 CCO=LOGICL
FCW=037f FSW=0000 [ST=0] FTW=00 MXCSR=00001f80
FPR0=0000000000000000 0000 FPR1=0000000000000000 0000
FPR2=0000000000000000 0000 FPR3=0000000000000000 0000
FPR4=0000000000000000 0000 FPR5=0000000000000000 0000
FPR6=0000000000000000 0000 FPR7=0000000000000000 0000
XMM00=00000000000000000000000000000000 XMM01=00000000000000000000000000000000
XMM02=00000000000000000000000000000000 XMM03=00000000000000000000000000000000
XMM04=00000000000000000000000000000000 XMM05=00000000000000000000000000000000
XMM06=00000000000000000000000000000000 XMM07=00000000000000000000000000000000

This application has requested the Runtime to terminate it in an unusual way.
    


Thanks in advance for any help!
Post 21 Jan 2010, 23:28
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edfed



Joined: 20 Feb 2006
Posts: 4242
Location: 2018
edfed
why don't you try to do the simple 4MB paging before the complex 4kB?

with 4MB pages, you don't need to create a lot of tables. only one is enough to catch the mecanism and understand how it works.

i stated to read the new IA32 manuals, the explanations are very clear now ( better than in PIV manuals..).

http://www.intel.com/Assets/PDF/manual/253668.pdf
here, at the paging section, you will see very cool infos and explanations:




Vol. 3 4-7 wrote:

The following items give an example for each of the three paging modes (each
example locates a 4-KByte page frame):
• With 32-bit paging, each paging structure comprises 1024 = 210 entries. For this
reason, the translation process uses 10 bits at a time from a 32-bit linear
address. Bits 31:22 identify the first paging-structure entry and bits 21:12
identify a second. The latter identifies the page frame. Bits 11:0 of the linear
address are the page offset within the 4-KByte page frame. (See Figure 4-2 for
an illustration.)
• With PAE paging, the first paging structure comprises only 4 = 22 entries.
Translation thus begins by using bits 31:30 from a 32-bit linear address to
identify the first paging-structure entry. Other paging structures comprise


to see paging working efficientlly in 4KB mode, you need:
1024+1024*1024 entries set. (4MB+4KB of memory occupied just to page...)
then, it is very simpler to do it in 4MB mode first. only 1024 entries are required.
Post 22 Jan 2010, 00:33
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egos



Joined: 10 Feb 2009
Posts: 144
egos
Quote:
why don't you try to do the simple 4MB paging before the complex 4kB?
This mechanism is less universal because it's not supported by some early IA-32 CPUs. The other reason is it needs be activated.

dosin, at first don't use last page(s) of base memory because it is EBDA.
Code:
;Set page dir: all to 0x00000007
xor eax,eax
xor edi,edi
xor ecx,ecx
        
mov edi,0x9C000
mov ecx,1024 
or eax,7 
@@: stosd 
loop @b    
Why did you this? Fill page dir with zeroes (or as I did).


Last edited by egos on 22 Jan 2010, 20:16; edited 1 time in total
Post 22 Jan 2010, 10:04
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edfed



Joined: 20 Feb 2006
Posts: 4242
Location: 2018
edfed
egos wrote:
This mechanism is less universal because it's not supported by any IA-32 CPUs. The other reason is it needs be activated.


the IA 32 manuals says:

IA32 supports 10 bits paging modes.
then, 4KB & 4MB paging.
the mode not supported by IA 32 is 2MB paging (IA32e), the 9bits paging

EBDA is BIOS related memory, it is not a CPU memory like IVT. when running IN PM, it is irrelevant like IVT.


the memory map for PM is not the same as the RM memory map.

Real mode memory map is a fixed type one, IVT is at linear 0, Bootstrap at linear 0FFFF0h, BIOS rom at linear 0FC000h, etc...

in PM, there is not any reserved (virtually) location, the cpu don't use any bootstrap or IVT in it's internals when running PMode.


IDT is located where the IDTR register points to (like GDTR, LDTR or TaskR)
in PM, no MEMORY is reserved to a special useage. you are free to locate anything where you want, in respect with memory mapped IO.

screen memory is one of then, it is not a direct memory, but it pass trough a IO port that will interpret the address as a selector (transparentlly) on the VGA chip address pins (I/O, not ram)

conclusion:
Real Mode memory is mapped by a norm
Protected Mode memory is not mapped, mapping is the task of the system programmer.
system programmer is free to map his memory as he wants.


Last edited by edfed on 22 Jan 2010, 17:00; edited 1 time in total
Post 22 Jan 2010, 11:18
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 17717
Location: In your JS exploiting you and your system
revolution
IIRC 4MB paging came in first on the Pentium. So 386 & 486 don't support it.
Post 22 Jan 2010, 11:34
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edfed



Joined: 20 Feb 2006
Posts: 4242
Location: 2018
edfed
but for now, everybody owns a pentium µP.
as it is simpler than 4KB paging, i recommend this one as a first step.
don't you?
Post 22 Jan 2010, 11:53
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f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
dosin wrote:
off subject question:

in Pmode - is there a way to get the full amount of system memory avail?
edfed wrote:
yep.
with paging.


i explain, the first thing to do with paging is:

set a page to memory linear 0
access memory 0 in the page
increment linear.
access memory 0 in the page
etc etc

when there is a page fault, it means there is no page at this place.

i think increment of 4MBytes can be good, then, a 4MB page is needed.
but you can also make a 4KB page.


don't forget to set a bitmap during memory test.

this test can be done with no paging, with a direct access to memory.
but now, you will read it, wrtie it, read it, restore it
read it
and maybe some cases will be problematic.
Indeed it is problematic, and I'd advise strongly against attempting to do this. Think about memory-mapped devices, various system tables (ACPI), ...

revolution wrote:
IIRC 4MB paging came in first on the Pentium. So 386 & 486 don't support it.
Oh, I always thought PSE was introduced with the PPro, but wiki says it was indeed introduced with the Pentium (though not documented before PPro). PAE was introduced with PPro, though Sad
Post 22 Jan 2010, 15:26
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egos



Joined: 10 Feb 2009
Posts: 144
egos
edfed wrote:
EBDA is BIOS related memory, it is not a CPU memory like IVT. when running IN PM, it is irrelevant like IVT.
EBDA contains important info for PM.
Quote:
the memory map for PM is not the same as the RM memory map.
Physical mem map is identical for both modes, but usually IVT and BDA (not EBDA) are not used in PM.
Quote:
as it is simpler than 4KB paging, i recommend this one as a first step.
I don't.
Post 22 Jan 2010, 15:26
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egos



Joined: 10 Feb 2009
Posts: 144
egos
edfed wrote:
bullshit wrote:
Shut up your mouth frenzied man.
Post 22 Jan 2010, 16:24
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edfed



Joined: 20 Feb 2006
Posts: 4242
Location: 2018
edfed
egos wrote:
edfed wrote:
bullshit wrote:
Shut up your mouth frenzied man.


please, just be correct. me too i know a lot of insults...
i did not told you that YOU are bullshit, just that the bullshit quote is a bullshit. bug fixed?

to modos, last two messages (egos and this one) are to be deleted.please
Post 22 Jan 2010, 16:43
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edfed



Joined: 20 Feb 2006
Posts: 4242
Location: 2018
edfed
Quote:

Indeed it is problematic, and I'd advise strongly against attempting to do this. Think about memory-mapped devices, various system tables (ACPI), ...

then, only a single read of memory can be enough.

PIV manual wrote:

If the page containing the linear address is not currentlly in physical memory, the processor generates a page-fault exception (#PF).

The exception handler for a PF tipically redirects the OS to load a page from disk storage.

then, a handler to just set current page as non-present in the memory map, or the page directory, can be enough.
Post 22 Jan 2010, 16:59
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f0dder



Joined: 19 Feb 2004
Posts: 3170
Location: Denmark
f0dder
edfed wrote:
f0dder wrote:
Indeed it is problematic, and I'd advise strongly against attempting to do this. Think about memory-mapped devices, various system tables (ACPI), ...
then, only a single read of memory can be enough.
Back in the port-I/O days, iirc port reading could "make stuff happen" on a device (e.g., consume and input byte and make next byte ready). Don't know if the same could happen with memory-mapped devices...

Also, you'll want to know not just that you can access a piece of memory with causing a #PF, you'll want to know whether it's RAM that's usable for your needs... read-scanning would simply determine that the memory is accessible, and you'd then add it to your "list of available ram". Also, you can't make any assumptions on where devices are going to be mapped, nor that physical memory is going to be contiguously mapped (iirc PCI devices are limited to do DMA in the lower 4GB memory space, so BIOSes have support for remapping physical memory above the 4GB mark. This is the reason why some machines running 32bit Windows will only see 2GB even if you have 4GB installed).

Also, consider how big an address space you would have to probe - even 32bit systems can support up to 64GB memory with PAE.

edfed wrote:
PIV manual wrote:
If the page containing the linear address is not currentlly in physical memory, the processor generates a page-fault exception (#PF).

The exception handler for a PF tipically redirects the OS to load a page from disk storage.
then, a handler to just set current page as non-present in the memory map, or the page directory, can be enough.
In conjunction with the memory probing method, or what do you mean?

AFAIK the safest bet is to rely on BIOS function E820 to query the system memory map... or falling back to E801 (or even 8Cool if it's not available.
Post 22 Jan 2010, 17:34
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egos



Joined: 10 Feb 2009
Posts: 144
egos
edfed wrote:
bug fixed?
What's bug?

Quote:
to modos, last two messages (egos and this one) are to be deleted.please
Why? Let everybody see this small talk Cool
Post 22 Jan 2010, 18:23
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edfed



Joined: 20 Feb 2006
Posts: 4242
Location: 2018
edfed
if you want
moderators, please, some posts in this thread needs to be deleted form this post for their offtopicness of the thread and the post yeah baby! thanks.
Post 22 Jan 2010, 18:49
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