Description  Browsers (with how-to-print informations)

General and System Opcodes  2-byte Opcodes  x87 FPU Opcodes  Instruction Extensions Opcodes

General and System Opcodes
p1 p2 po so flds mod o proc st  m rl l mnemonic    op1  op2  op3  iext group1 group 2 group 3 tested f modif f  def f    undef f  f values description, notes                                               
00 dw r 00+ D R 3 L ADD Eb Gb gen arith binary o..szapc o..szapc Add
01 dW r 00+ D R 3 L ADD Evqp Gvqp gen arith binary o..szapc o..szapc Add
02 Dw r 00+ D R 3 L ADD Gb Eb gen arith binary o..szapc o..szapc Add
03 DW r 00+ D R 3 L ADD Gvqp Evqp gen arith binary o..szapc o..szapc Add
04 w 00+ D R 3 ADD AL Ib gen arith binary o..szapc o..szapc Add
05 W 00+ D R 3 ADD rAX Ivds gen arith binary o..szapc o..szapc Add
06 sr 00+ D R 3 PUSH ES gen stack segreg Push Word, Doubleword or Quadword Onto the Stack
64E+ invalid Invalid Instruction in 64-Bit Mode
07 sr 00+ D R 3 POP ES gen stack segreg Pop a Value from the Stack
64E+ invalid Invalid Instruction in 64-Bit Mode
08 dw r 00+ D R 3 L OR Eb Gb gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
09 dW r 00+ D R 3 L OR Evqp Gvqp gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0A Dw r 00+ D R 3 L OR Gb Eb gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0B DW r 00+ D R 3 L OR Gvqp Evqp gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0C w 00+ D R 3 OR AL Ib gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0D W 00+ D R 3 OR rAX Ivds gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0E sR 00+ D R 3 PUSH CS gen stack segreg Push Word, Doubleword or Quadword Onto the Stack
64E+ invalid Invalid Instruction in 64-Bit Mode
0F 00 D1 POP CS gen stack segreg Pop a Value from the Stack
01 D invalid
0F 02+ 2-byte Opcodes
10 dw r 00+ D R 3 L ADC Eb Gb gen arith binary .......c o..szapc o..szapc Add with Carry
11 dW r 00+ D R 3 L ADC Evqp Gvqp gen arith binary .......c o..szapc o..szapc Add with Carry
12 Dw r 00+ D R 3 L ADC Gb Eb gen arith binary .......c o..szapc o..szapc Add with Carry
13 DW r 00+ D R 3 L ADC Gvqp Evqp gen arith binary .......c o..szapc o..szapc Add with Carry
 
26 00+ D ES pref segreg ES segment override prefix
P4+ reserved branch (use with any branch instruction is reserved)
64E+ null segreg Null Prefix in 64-bit Mode.
27 00+ D R 3 DAA gen arith decimal .....a.c o..szapc ...szapc o....... Decimal Adjust AL after Addition
64E+ invalid Invalid Instruction in 64-Bit Mode
 
2E 00+ D CS pref segreg ES segment override prefix
P4+ no mnemonic (NTAKEN) branch Branch not taken prefix (used only with Jcc instructions)
64E+ null segreg Null Prefix in 64-bit Mode.
 
40 00+ D R 3 INC eAX gen arith binary o..szap. o..szap. Increment by 1
40 64E+ no mnemonic pref rex
41 00+ D R 3 INC eCX gen arith binary o..szap. o..szap. Increment by 1
41 64E+ REX.B pref rex 1-bit extension of the r/m field, base field, or opcode reg field
 
50 +r 00+ D R 3 PUSH Zvq gen stack Push Word, Doubleword or Quadword Onto the Stack
 
62 D r 00+ D R f BOUND Gv Ma gen branch int ODISZAPC ..I..... ..I..... ..I..... Check Array Index Against Bounds
64E+ invalid Invalid Instruction in 64-Bit Mode
63 r 00+ D P 3 ARPL Ew Gw system ....z... ....z... Adjust RPL Field of Segment Selector
D 64E+ R MOVSXD Gqp Eds gen conver Move with Sign-Extension
64 03+ D FS pref segreg ES segment override prefix
P4+ reserved branch (use with any branch instruction is reserved)
U2 no mnemonic (ALTER) Alternating branch prefix (used only with Jcc instructions)
65 03+ D GS pref segreg GS segment override prefix
P4+ reserved branch (use with any branch instruction is reserved)
66 00+ D no mnemonic pref Operand-size override prefix
P4+ M sse2 Precision-size override prefix
 
6E w 01+ D R f1 OUTS OUTSB DX Xb gen inout string .d...... Output String to Port
6F W 01+ D R f1 OUTS OUTSW DX Xv gen inout string .d...... Output String to Port
03+ OUTS OUTSD
70 tttn 00+ D R 3 JO Jb gen branch o....... Jump short if overflow (OF=1)
71 tttN 00+ D R 3 JNO Jb gen branch o....... Jump short if not overflow (OF=0)
72 ttTn 00+ D R 3 JB/NAE/C Jb gen branch .......c Jump short if below/not above or equal/carry (CF=1)
 
80 w 0 00+ D R 3 L ADD Eb Ib gen arith binary o..szapc o..szapc Add
80 w 1 00+ D R 3 L OR Eb Ib gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
80 w 2 00+ D R 3 L ADC Eb Ib gen arith binary .......c o..szapc o..szapc Add with Carry
80 w 3 00+ D R 3 L SBB Eb Ib gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
80 w 4 00+ D R 3 L AND Eb Ib gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
80 w 5 00+ D R 3 L SUB Eb Ib gen arith binary o..szapc o..szapc Subtract
80 w 6 00+ D R 3 L XOR Eb Ib gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
80 w 7 00+ D R 3 L CMP Eb Ib gen arith binary o..szapc o..szapc Compare Two Operands
 
82 w 0 00+ D R 3 L ADD alias Eb Ib gen arith binary o..szapc o..szapc Add
82 w 1 00+ D R 3 L OR alias Eb Ib gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
82 w 2 00+ D R 3 L ADC alias Eb Ib gen arith binary .......c o..szapc o..szapc Add with Carry
82 w 3 00+ D R 3 L SBB alias Eb Ib gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
82 w 4 00+ D R 3 L AND alias Eb Ib gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
82 w 5 00+ D R 3 L SUB alias Eb Ib gen arith binary o..szapc o..szapc Subtract
82 w 6 00+ D R 3 L XOR alias Eb Ib gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
82 w 7 00+ D R 3 L CMP alias Eb Ib gen arith binary o..szapc o..szapc Compare Two Operands
82 64E+ invalid Invalid Instruction in 64-Bit Mode
 
90 +r 00+ D R 3 XCHG Zvqp rAX gen datamov Exchange Register/Memory with Register
NOP       control No Operation
F3      
P4+ PAUSE Spin Loop Hint
 
9B 00+ D R 3 WAIT FWAIT x87fpu control 0123 0123 Wait
9C 00+ D R 3 PUSHF Fw gen stack flgctrl odiszapc Push rFLAGS Register onto the Stack
03+ PUSHF/ PUSHFD Fv
64E+ PUSHF/ PUSHFQ Fvq
 
C0 w 0 01+ D R 3 ROL Eb Ib gen shftrot o..szapc O..szapc O....... Rotate
C0 w 1 01+ D R 3 ROR Eb Ib gen shftrot o..szapc O..szapc O....... Rotate
C0 w 2 01+ D R 3 RCL Eb Ib gen shftrot .......c o..szapc O..szapc O....... Rotate
C0 w 3 01+ D R 3 RCR Eb Ib gen shftrot .......c o..szapc O..szapc O....... Rotate
C0 w 4 01+ D R 3 SHL SAL Eb Ib gen shftrot O..szapc O..sz.pc .....a.. Shift
C0 w 5 01+ D R 3 SHR Eb Ib gen shftrot O..szapc O..sz.pc .....a.. Shift
C0 w 6 01+ U3 R 3 SAL SHL alias Eb Ib gen shftrot O..szapc O..sz.pc .....a.. Shift
C0 w 7 01+ D R 3 SAR Eb Ib gen shftrot O..szapc O..sz.pc .....a.. Shift
 
C3 00+ D R 3 RET gen branch near Return from Procedure
 
CB 00+ D R f RET gen branch far Return from Procedure
CC 00+ D R f INT 3 gen branch int odiszapc ..i..... ..i..... ..i..... Call to Interrupt Procedure
CD 00+ D R f INT Ib gen branch int odiszapc ..i..... ..i..... ..i..... Call to Interrupt Procedure
 
D4 0A 00+ D R 3 AAM gen arith decimal o..szapc ...sz.p. o....a.c ASCII Adjust AX After Multiply
no mnemonic (AM) Ib Adjust AX after multiply
64E+ invalid Invalid Instruction in 64-Bit Mode
D5 0A 00+ D R 3 AAD gen arith decimal o..szapc ...sz.p. o....a.c ASCII Adjust AX Before Division
no mnemonic (AD) Ib Adjust AX Before Division
64E+ invalid Invalid Instruction in 64-Bit Mode
D6 02+ D4 undefined Undefined and Reserved; Does not Generate #UD
02+ U5 R 3 SALC SETALC .......c Set AL If Carry
64E+ D invalid Invalid Instruction in 64-Bit Mode
D7 00+ D R 3 XLAT XLATB gen datamov Table Look-up Translation
D8- DF 00+ D R 3 x87 FPU Opcodes
 
F1 03+ D4 undefined Undefined and Reserved; Does not Generate #UD
U5 R ? INT1 ICEBP partial6 alias gen branch int odiszapc ..i..... ..i..... ..i..... Call to Interrupt Procedure
x87 FPU Opcodes
p1 p2 po so flds mod o proc st  m rl l mnemonic    op1  op2  op3  iext group1 group 2 group 3 tested f modif f  def f    undef f  f values description, notes                                               
D8 mf ≠11 0 00+ D R 3 FADD Msr x87fpu arith 0123 .1.. 0.23 Add
=11 ST STi
D8 mf ≠11 1 00+ D R 3 FMUL Msr x87fpu arith 0123 .1.. 0.23 Multiply
=11 ST STi
D8 mf ≠11 2 00+ D R 3 FCOM Msr x87fpu arith 0123 .1.. 0.23 Compare Floating Point Values
=11 ST STi
D8 mf ≠11 3 00+ D R 3 FCOMP Msr x87fpu arith 0123 .1.. 0.23 Compare Floating Point Values
=11 ST STi
D8 mf ≠11 4 00+ D R 3 FSUB Msr x87fpu arith 0123 .1.. 0.23 Subtract
=11 ST STi
D8 mf ≠11 5 00+ D R 3 FSUBR Msr x87fpu arith 0123 .1.. 0.23 Reverse Subtract
=11 ST STi
D8 mf ≠11 6 00+ D R 3 FDIV Msr x87fpu arith 0123 .1.. 0.23 Divide
=11 ST STi
D8 mf ≠11 7 00+ D R 3 FDIVR Msr x87fpu arith 0123 .1.. 0.23 Reverse Divide
=11 ST STi
 
DB mF ≠11 0 00+ D R 3 FILD Mdi x87fpu datamov 0123 .1.. 0.23 Load Integer
=11 PP+ FCMOVNB ST STi .......c Floating-Point Conditional Move
DB mF ≠11 1 P4++ D R 3 FISTTP Mdi sse3 x87fpu conver 0123 .1.. 0.23 .0.. Store Integer with Truncation
=11 PP+ FCMOVNE ST STi datamov ....z... 0123 .1.. 0.23 Floating-Point Conditional Move
DB mF ≠11 2 00+ D R 3 FIST Mdi x87fpu datamov 0123 .1.. 0.23 Store Integer
=11 PP+ FCMOVNBE ST STi ....z..c Floating-Point Conditional Move
DB mF ≠11 3 00+ D R 3 FISTP Mdi x87fpu datamov 0123 .1.. 0.23 Store Integer
=11 PP+ FCMOVNU ST STi ......p. Floating-Point Conditional Move
DB ≠11 4 00+ invalid
E0 =11 00 D R 3 FNENI x87fpu control ? ? ? ? Enable NPX Interrupt
9B FENI
01+ FNENI nop7 obsol control Treated as Integer NOP
E1 00 FNDISI x87fpu control ? ? ? ? Disable NPX Interrupt
9B FDISI
01+ FNDISI nop7 obsol control Treated as Integer NOP
E2 00+ FNCLEX x87fpu control 0123 Clear Exceptions
9B FCLEX
E3 FNINIT 0123 0123 0000 Initialize Floating-Point Unit
9B FINIT
E4 02 FNSETPM ? ? ? ? Set Protected Mode
9B FSETPM
03+ FNSETPM nop7 obsol control Treated as Integer NOP
E5 02 U8 FRSTPM x87fpu control ? ? ? ? Reset Protected Mode
DB ≠11 5 00+ D R 3 FLD Mer x87fpu datamov 0123 .1.. 0.23 Load Floating Point Value
=11 PP+ FUCOMI ST STi compar ....z.pc
.1..
....z.pc
.1..
Compare Floating Point Values and Set EFLAGS
DB ≠11 6 00+ D R 3 invalid
=11 PP+ FCOMI ST STi x87fpu compar ....z.pc
.1..
....z.pc
.1..
Compare Floating Point Values and Set EFLAGS
DB ≠11 7 00+ D R 3 FSTP Mer x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value
=11 invalid
2-byte opcodes
p1 p2 po so flds mod o proc st  m rl l mnemonic    op1  op2  op3  iext group1 group 2 group 3 tested f modif f  def f    undef f  f values description, notes                                               
0F 00 ≠11 0 02+ D P 3 SLDT Mw system Store Local Descriptor Table Register
=11 Evqp
0F 00 ≠11 1 02+ D P 3 STR Mw system Store Task Register
=11 Evqp
0F 00 2 02+ D P 0 LLDT Ew system Load Local Descriptor Table Register
0F 00 3 02+ D P 0 LTR Ew system Load Task Register
0F 00 4 02+ D P 3 VERR Ew system ....z... ....z... Verify a Segment for Reading
0F 00 5 02+ D P 3 VERW Ew system ....z... ....z... Verify a Segment for Writing
0F 00 6 64I+ D ? 3 JMPE Ev ? ? Jump to IA-64 Instruction Set
0F 01 ≠11 0 02+ D R 3 SGDT Ms system Store Global Descriptor Table Register
C1 =11 P4++ ? VMCALL vmx O..SZAPC O..SZAPC Call to VM monitor
C2 VMLAUNCH Launch Virtual Machine
C3 VMRESUME Resume Virtual Machine
C4 VMXOFF Leave VMX Operation
0F 01 ≠11 1 02+ D R 3 SIDT Ms system Store Interrupt Descriptor Table Register
C8 =11 P4++ MONITOR sse3 sync Setup Monitor Address
C9 MWAIT Monitor Wait
0F 01 2 02+ D R 0 LGDT Ms system Load Global Descriptor Table Register
0F 01 3 02+ D R 0 LIDT Ms system Load Interrupt Descriptor Table Register
0F 01 ≠11 4 02+ D R 3 SMSW Mw system Store Machine Status Word
=11 Evqp
0F 01 5 invalid
0F 01 6 02+ D R 0 LMSW Ew system Load Machine Status Word
0F 01 ≠11 7 04+ D R 0 INVLPG M system Invalidate TLB Entry
F8 =11 64E+ P SWAPGS Swap GS Base Register
 
0F 10- 18 P3+ D R 3 Instruction Extensions Opcodes
 
0F 24 r 03- 04 D R 0 MOV Rd Td system o..szapc o..szapc Move to/from Test Register
0F 26 r 03- 04 D R 0 MOV Td Rd system o..szapc o..szapc Move to/from Test Register
Instruction Extensions Opcodes
p1 p2 po so flds mod o proc st  m rl l mnemonic    op1  op2  op3  iext group1 group 2 group 3 tested f modif f  def f    undef f  f values description, notes                                               
0F 10 r P3+ D R 3 MOVUPS Vps Wps sse1 simdfp datamov Move Unaligned Packed Single-Precision Floating-Point Values
F3 MOVSS Vss Wss Move Scalar Single-Precision Floating-Point Values
66 P4+ MOVUPD Vpd Wpd sse2 pcksclr datamov Move Unaligned Packed Double-Precision Floating-Point Values
F2 MOVSD Vsd Wsd Move Scalar Double-Precision Floating-Point Value
0F 11 r P3+ D R 3 MOVUPS Wps Vps sse1 simdfp datamov Move Unaligned Packed Single-Precision Floating-Point Values
F3 MOVSS Wss Vss Move Scalar Single-Precision Floating-Point Values
66 P4+ MOVUPD Wpd Vpd sse2 pcksclr datamov Move Unaligned Packed Double-Precision Floating-Point Values
F2 MOVSD Wsd Vsd Move Scalar Double-Precision Floating-Point Value
0F 12 ≠11 r P3+ D R 3 MOVLPS Vp Mq sse1 simdfp datamov Move Low Packed Single-Precision Floating-Point Values
=11 MOVHLPS Vps Vps Move Packed Single-Precision Floating-Point Values High to Low
66 P4+ MOVLPS Vp Mq sse2 pcksclr datamov Move Low Packed Single-Precision Floating-Point Values
F2 P4++ MOVDDUP Vq Wq sse3 simdfpd Move One Double-FP and Duplicate
F3 MOVSLDUP Vps Wps Move Packed Single-FP Low and Duplicate

General notes:

1 OPCODE.LST, Revision 4.51, 15 Oct 1999 © Potemkin's Hackers Group 1994...1999
2 How to optimize for the Pentium family of microprocessors, By Agner Fog, Ph.D., Copyright © 1996 - 2003
3 sandpile.org -- IA-32 architecture -- opcode groups
4 IA-32 Intel® Architecture Software Developer's Manual Volume 3: System Programming Guide, Interrupt and Exception Handling
5 AMD64 Architecture Programmer's Manual Volume 3, Table One-Byte Opcodes
6 Christian Ludloff wrote: Unlike INT 1 (CDh,01h), INT1 (F1h) doesn't perform the IOPL or DPL check and it can't be redirected via the TSS32.IRB.
7 IA-32 Intel® Architecture Software Developer's Manual Volume 3: System Programming Guide, IA-32 Compatibility, x87 FPU
8 sandpile.org -- IA-32 architecture -- ESC (FP) opcodes

Notes for the Ring Level, used in case of f mark:

1 rFlags.IOPL
2 CR4.TSD (bit 2)

Columns description:

p1 p2 po so flds mod o proc st  m rl l mnemonic    op1  op2  op3  iext group1 group 2 group 3 tested f modif f  def f    undef f  f values description, notes                                               
Fixed Prefix 1, 2
Both prefixes don't always match the meaning of a prefix from the Intel manuals. These are simply the values which always precede the primary opcode.
• prefix 2 is often the first byte of 2-byte opcodes (0Fhex), prefix 1 holds a prefix of SSEs then
• prefix 2 holds the opcode of WAIT (FWAIT) instruction in case of waiting x87 FPU instructions
• prefix 2 holds a preceding value in some special cases (e.g. PAUSE)

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Primary Opcode
1. Basic opcode. It is always present if the value is not a prefix.
2. Lower limit of skipped opcode range, if the Mnemonic column contains a reference to an opcode group (e.g. x87 FPU opcodes).

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Secondary Opcode
1. Fixed appended value to the primary opcode.
   Used:
   • with some of x87 FPU instructions
   • with some of new instructions (e.g. VMX instruction extensions)
   • in some special cases (e.g. AAM or AAD instruction)
2. The higher limit of skipped opcode range.

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Opcode Fields
The marking of present primary opcode bit fields:
case insensitive:
• +r means a register code, from 0 through 7, added to the basic value of the primary opcode
case sensitive: if a letter of the marking is lower-case, it means the appropriate bit is cleared, otherwise is set
• w means bit w (bit index 0, operand size) is present; may be combined with bits d and s
• s means bit s (bit index 1, Sign-extend); may be combined with bit w
• d means bit d (bit index 1, Direction); may be combined with bit w
• tttn means bit field tttn (4 bits, bit index 0, condition); used only with conditional instructions
• sr means segment register specifier - a code of original four segment registers (2 bits, bit index 3)
• sre means segment register specifier - a code of all segment registers (3 bits, bit index 0 or 3)
• mf means bit field MF - memory format (2 bits, bit index 1); used only with x87 FPU instructions coded with second floating-point instruction format

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Mod Field
The value of the Mod field in ModR/M byte.
Used:
• most often with x87 FPU instructions
• some of newer instructions (e.g. SFENCE, CLFLUSH)
• in some special cases, when the operand type or mnemonic changes according to this value (e.g. SMSW, MOVLPS/MOVHLPS)

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Register/Opcode Field
The value of the opcode extension (values from 0 through 7) or indicates using r mark that the ModR/M byte contains a register operand and an r/m operand.

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Introduced with the Processor
Marks the processor of the instruction introduction:
• 00 8086
• 01 80186
• 02 80286
• 03 80386
• 04 80486
• P0 Pentium (plain)
• PP Pentium Pro
• P2 Pentium II
• P3 Pentium III
• P4 Pentium 4
• 64E Intel Processor with Extended Memory 64-bit Technology
• 64I Intel Itanium Processor (only JMPE)
Optional markings, which may follow the main marking:
• if the processor marking is a range (e.g. 03-04), it means that the instruction is unsupported in next generations of the processor (only the Move to/from Test Register instruction)
• + (e.g. 00+) the instruction is supported in any of posterior processors, including 64E processor, if the next row doesn't explicitly say otherwise (e.g. PUSH ES)
• ++ (e.g. P4++) same meaning, but only in the latter steppings of the processor (e.g. SSE3 instruction extensions)

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Status
Marks how is the instruction documented in the Intel manuals:
• D fully documented; it can contain a reference to and a title with the chapter, where the instruction is documented, if it may be unclear
• M only marginally (e.g. meaning of prefix 66hex when used with SSE instruction extensions)
• U undocumented at all; it should contain a reference to and a title with the source (e.g. SALC, INT1)

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Mode of Operation
Marks the mode, in which is the instruction valid:
• R valid in real and protected mode; SMM is not taken into account
• P valid only in protected mode; SMM is not taken into account
• S valid only in SMM (only RSM)

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Ring Level
The ring level, from which is the instruction valid (3 or 0), or indicates using f mark that the level depends on a flag(s) (e.g. IN: rFLAGS.IOPL).
It should contain a title with and a reference to the description of that flag, if the flag is not complex. The title is useful in electronic use, the reference is necessary in printed version.

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Lock Prefix
If the instruction is not valid with the lock prefix, this column is blank, otherwise it holds L mark.

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Instruction Mnemonic
1. The instruction mnemonic itself. It is followed by alternative mnemonic (e.g. WAIT-FWAIT), if any.
   If there is no mnemonic, it holds additional information about the mnemonic or instruction:
   • no mnemonic there is no mnemonic for the opcode (e.g. some of prefixes); can be followed by my suggestion in parentheses
   • invalid the opcode is invalid; this option is not used everywhere the opcode is invalid, but only in some cases
   • undefined the behaviour of the instruction is undefined (e.g. SALC)
   • null (only prefixes) the prefix has no meaning (no operation)
   If there is a mnemonic, it can hold additional attributes of the instruction:
   • alias the instruction is an alias to another instruction (e.g. SAL); the attribute should be a reference to that instruction and the title should contain the referenced opcode
   • partial alias means not true alias (e.g. INT1); it should contain a reference to and a title with the differences between referenced instructions
   • nop the instruction is treated as integer NOP instruction (only obsolete x87 FPU instructions); it should contain a reference to and the title with the source
2. A reference to an instruction group (e.g. x87 FPU opcodes).

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Operand 1, 2, 3
The code of the first, second and third operand, if any. These codes are the same like those ones used in the Opcode Map in the Intel manual.
If the code is printed using italic, the operand is not explicitly present in the instruction (e.g. FCOM with mod=11).
There are additionally the following codes:
for general-purpose instructions
• Z addressing method: new method; means:
  The instruction has no ModR/M byte; the three least-significant bits of the opcode byte selects a general-purpose register
• vqp operand type: combines v and qp types and means:
  Word or doubleword, depending on operand-size attribute, or quadword, promoted by REX.W, if REX is applicable
• vds operand type: combines v and ds types and means:
  Word or doubleword, depending on operand-size attribute, or doubleword, sign-extended to 64 bits, if such extension is applicable
for x87 FPU instructions
• wi operand type: word-integer
• di operand type: dword-integer
• qi operand type: qword-integer
• sr operand type: single-real
• dr operand type: double-real
• er operand type: extended-real
• e operand type: 14/28 bytes (only FPU environment)
• s operand type: 94/108 bytes (only FPU state)
• bcd operand type: 80-bit packed-BCD

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Instruction Extension Group
The instruction extension group, in which was the instruction released:
• MMX MMX technology
• SSE1 Streaming SIMD extensions
• SSE2 Streaming SIMD extensions 2
• SSE3 Streaming SIMD extensions 3
• VMX Virtualization Technology extensions

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Main Group (Group1), Sub-group (Group 2), Sub-sub-group (Group 3)
Classifies the instruction among groups. These group don't match the instruction groups given by the Intel manual. One instruction may fit into more groups.

The pattern used in the list:

• main group name full name
 · sub-group name full name
  - sub-sub-group name full name

• pref prefix
 · segreg segment register
 · branch branch
 · rex REX prefixes

• obsol obsolete
 · control control

• gen general-purpose
 · datamov data movement
 · stack stack
 · conver type conversion
 · arith arithmetic
  - binary binary
  - decimal decimal
 · logical logical
 · shftrot shift&rotate
 · bit bit manipulation
 · branch branch
  - near near (defined because RET instructions don't have this information in the mnemonic)
  - far far (same reason)
  - int interrupt (defined because in case of BOUND it is not clear)
 · string string
 · inout I/O
 · flgctrl flag control
 · segreg segment register manipulation
 · control control (e.g. NOP, UD2, CPUID)

• system system

• x87FPU x87 FPU
 · datamov data movement
 · arith basic arithmetic
 · compar comparison
 · trans transcendental
 · ldconst load constant
 · control control
 · conversion conversion (only FISTTP (SSE3))

• sm x87 FPU and SIMD state management

• for MMX instruction extensions
 · datamov data movement
 · arith packed arithmetic
 · compar comparison
 · logical logical
 · shift shift
 · stmanag state management

• for SSE1 instruction extensions
 · simdfp SIMD single-precision floating-point
  - datamov data movement
  - conver conversion
  - arith packed arithmetic
  - compar comparison
  - logical logical
  - shunpck shuffle&unpack
 · simdint 64-bit SIMD integer
  - shuffle shuffle
  - average compute average
  - word WORD operation
  - minmax minimum or maximum
 · mxcsrsm MXCSR state management
 · cachect cacheability control
 · pref prefetch
 · order instruction ordering

• for SSE2 instruction extensions
 · pcksclr packed and scalar double-precision floating-point
  - datamov data movement
  - conver conversion
  - arith packed arithmetic
  - compar comparison
  - logical logical
  - shunpck shuffle&unpack
 · pcksp packed single-precision floating-point
 · simdint 128-bit SIMD integer
  - datamov data movement
  - arith packed arithmetic
  - shunpck shuffle&unpack
  - shift shift
 · mxcsrsm MXCSR state management
 · cachect cacheability control
 · order instruction ordering

• for SSE3 instruction extensions
 · simdfp SIMD single-precision floating-point (SIMD packed)
 · simdfph SIMD double-precision floating-point horizontal
 · simdfpd SIMD floating-point duplicate
 · cachect cacheability control (only LDDQU)
 · sync agent synchronization

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Tested, Modified, Defined, and Undefined Flags
for the rFlags register:
Marks these flags using case-sensitive o d i s z a p c flag pattern. Present flag fits in with the appropriate group.
If a flag is upper-case, the flag fits in only under next conditions (e.g. OF in shift&rotate instructions)
for the x87 FPU flags:
Marks these flags using 0 1 2 3 FPU flag pattern. Present flag fits in with the appropriate group.

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Flags Values
for the rFlags register:
Marks the values of flags, which are always set or cleared, using case-sensitive o d i s z a p c flag pattern.
Lower-case flag means cleared flag, upper-case means set flag.
for the x87 FPU flags:
Marks these flags using 0 1 2 3 FPU flag pattern. Present flag holds its value.

p1 p2 po so flds mod o proc st m rl l mnemonic op1 op2 op3 iext group1 group 2 group 3 tested f modif f def f undef f f values description, notes
Description, Notes
Contains the instruction's general description or some general notes.

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