is there any cache for IDT in newer processors? (so that could fasten interrupts)

i never heard about that,
but i think, that interrupts are usually not so often taken, so that a cache wouldn't imprvoe performance.(well, a amount off 200 Int's a second isn't very much for a today CPU)

Well, I'm not an AMD chip architect, and I don't know the answer to your question.

I do know that the "int" instruction causes a jump into ring 0, which causes a rather large performance penalty, on the order of 100-900 cycles.

I thought PL3 as well as conforming-code interrupts were possible, depending on how the IDT slots were set up?

And depending on the IOPL field as well right?

If there was cache, i think there would also be need for syncing the cache after modifying IDT in memory - and I have never heard about that.