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Index > Main > Segment Access Rights in Segment Descriptor Cache in Present

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Pinczakko



Joined: 02 May 2004
Posts: 34
Location: Takabonerate National Park, Indonesia
Pinczakko
According to http://www.rcollins.org/ddj/Aug98/Aug98.html article,
the "access rights" (G, D/B, P, DPL, S and Type bits) and the limit bits
in the segment descriptor cache are "honored" (not changed) even if the segment
register value is changed in real mode (16-bit)--only the base address bits are changed.
Well, of course this scenario excludes reloading the descriptor cache by "switching to Protected mode".

Is this fact still holds true in present day x86 CPUs?
I mean the details of the venerable "Unreal-Mode" doesn't change Smile.

Anyway, I'm particularly concerned about the segment-access-rights bits.

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Post 12 Apr 2012, 17:20
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16890
Location: In your JS exploiting you and your system
revolution
Pinczakko wrote:
Is this fact still holds true in present day x86 CPUs?
I mean the details of the venerable "Unreal-Mode" doesn't change Smile.
If things had changed then much code would now be failing.
Pinczakko wrote:
Anyway, I'm particularly concerned about the segment-access-rights bits.
One way to find out is to test it.
Post 12 Apr 2012, 21:01
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