Message board for the users of flat assembler.
> Main > absolute addressing in long mode
Feryno 28 Oct 2023, 18:55
While constructing very fast disasm engine which returns only instruction size (needed for an APIC emulator inside hypervisor), I studied CPU manuals again (AMD as well Intel) and I came across this thing. FASM version 1.71.22 generates correctly these opcodes:
mov [qword 0FEE00000h],eax -> A30000E0FE00000000
mov [dword 0FEE00000h],eax -> 67A30000E0FE
In CPU manuals I found a third way how to encode absolute addressing mode:
mod = 00, r/m = 100, SIB. base = 101 (none), SIB.index = 100 (none), SIB.scale = 0, 1, 2, 4
I was unable to tell FASM how to compile this way (is this possible?) so I encoded it manually as:
8904250000E0FE -> mov [FFFFFFFFFEE00000],eax
note in this case CPU sign extends the dword address
Or someone may develop a macro for that using this formula:
; mod = 00, r/m = 100, SIB.base = 101, SIB.index = 100, SIB.scale=xx
db 89h, 100b, 00100101b, 00h, 00h, 0E0h, 0FEh
db 89h, 100b, 01100101b, 00h, 00h, 0E0h, 0FEh
db 89h, 100b, 10100101b, 00h, 00h, 0E0h, 0FEh
db 89h, 100b, 11100101b, 00h, 00h, 0E0h, 0FEh
There is nothing to solve, FASM generates fine code using first 2 choices. I just came across the third way which is very likely useless for FASM compiler, but should be taken into consideration when writing a disassembler/emulator etc.
|28 Oct 2023, 18:55||
Tomasz Grysztar 28 Oct 2023, 19:50
I think it's what was discussed here: https://board.flatassembler.net/topic.php?p=211682#211682
Current versions of fasm assemble the examples given there the same way as the fasmg-based prototype.
|28 Oct 2023, 19:50||
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