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flat assembler > Main > Question about GDT Table endianness

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Ben321



Joined: 07 Dec 2017
Posts: 57
Is it big endian? It looks like bit 31 (which represents the value 2^31, and is part of the 4th byte of a DWord) comes before bit 0 (which is in the first byte of a DWord), in this image
Image

However it is my understanding that Intel CPUs are actually little endian devices. So when I'm writing code for setting the GDT (my file is going to need to contain the GDT's bytes), how should I actually lay out the bytes in the file? Should the most significant byte come before or after the least significant byte?
Post 01 Oct 2018, 23:29
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alexfru



Joined: 23 Mar 2014
Posts: 66
All are little endian.
Post 02 Oct 2018, 08:13
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Furs



Joined: 04 Mar 2016
Posts: 1315
Humans write and read numbers backwards -- not like how we write words left-to-right, but from right-to-left (which is how arabs write words and where they are from...).

Once you understand this simple fact, you'll know why Little Endian is just the right way and it's our number notation that's wrong.

With bytes, lower memory address is on the left. Higher address is on the right. Why shouldn't it be the same with bits? In fact, that's exactly how little-endian encodes everything: left-to-right, lowest-to-highest.

Big Endian is the only crap that's "mixed" and just seems "arbitrary". I'm so glad it's mostly dead, it pains me to see technical prowess dragged down by human idiocy.
Post 02 Oct 2018, 15:10
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DimonSoft



Joined: 03 Mar 2010
Posts: 451
Location: Belarus
Furs wrote:
Big Endian is the only crap that's "mixed" and just seems "arbitrary". I'm so glad it's mostly dead, it pains me to see technical prowess dragged down by human idiocy.

It is still quite widespread though, remember that it is also sometimes a synonym of “network byte order”. Certain protocols still use this endianness. Even PNG uses BE, IIRC.
Post 02 Oct 2018, 15:35
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Furs



Joined: 04 Mar 2016
Posts: 1315
Yes, there's nothing much you can do about that, since it would break compatibility. I mean in new designs and such.
Post 02 Oct 2018, 16:47
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Ben321



Joined: 07 Dec 2017
Posts: 57
I have noticed that even if the biggest byte should be on the right for little endian, it appears to be on the left in the diagram. For example the low order bits of the Base field, clearly show bit 16 being on the right, and bit 16 being on the left. So I assume that that 16bit integer field is split into 2 bytes, arranged in big endian byte order.

But then the question is this. Does that just show the internal physical arrangement of the bits in the CPU? Or does this diagram accurately show the layout of the data as it would need to be written into an executable file.

Also, there's different notations for righting bits within a byte. Some use "bit 7" to just mean "farther to the left" or "farther to the right" than "bit 0" in the diagram (with no specific numerical meaning. While others specifically mean the value the bit represents is 2^BitNumber (and whatever order they are shown in in the diagram doesn't matter within each byte, but it will matter for endianness when arranging bytes if the bit field is shown to cross byte boundaries). And because there's so many notations within the community for graphically showing the layout of data structures, it's hard to know when actually IMPLEMENTING the structure (like when I'm trying to write an ASM program that uses it) exactly WHERE the different fields are in relation to each other (like within the overall data structure, which field is byte0, byte1, byte2, etc). And yes, I need it to be broken down into individual bytes (not multibyte integers, as those can have their bytes arranged in any order, unless the textual documentation surrounding the diagram image on the webpage explicitly states how the bits and bytes are arranged, so I know EXACTLY how to interpret the diagram).

I wish there was one definitive diagram that showed "when writing a program using this structure, make sure this field is the first byte, then that field is the second byte, ..."

I mean just look at this. Here's 2 completely different diagrams, that show 2 completely different ways that a GDT entry's fields are arranged. Only ONE of these is correct, and I don't know which one.

Image
Image
Post 02 Oct 2018, 19:50
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DimonSoft



Joined: 03 Mar 2010
Posts: 451
Location: Belarus
Ben321 wrote:
Image
Image

The first one is from Intel’s SDM, i.e. official documentation. The second one seems to be something from the Internet, I guess? When you use Internet as your main source of information, you get what you deserve: all sorts of inconsistent notations.

Anyway, Intel’s documentation clearly specifies that the entry may be interpreted as two dwords, the lower one (placed at offset 0) having one half for 16 bits of segment limit and one half for 16 bits of base address, and the higher one (offset 4) containing the rest of the information. Bits inside the dwords are clearly numbered as if they’re bits inside dwords. And Intel SDM clearly states that bit 0 is always the least-significant one and that endianness is always LE, i.e. dwords are written in LE way.

The Internet picture is not that bad as well. It definitely uses mixed endianness but at least the numbering of bits clearly explains the order of the fields for when you treat the entry as a single 64-bit value.
Post 03 Oct 2018, 00:27
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16127
Location: Hyperborea
Everything Intel is 100% little endian.
Post 03 Oct 2018, 03:16
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