hmm, I test it too now:

maybe it's related to opcode encoding? (eg, the "base reg" can't be the same as the "destination reg") -- haven't checked the opcode ref now.

Source: IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture, p. 70 (or, in their notation, 3-20)

After having read this thread, i took a look at the way RosAsm does it. Same problem, here. I just solved it by exchanging the two Registers, when wishable. I don't know how it is in FASM syntax, but, in RosAsm one, we can as well have the Base first or second (and Index second or first), so it seemed to me logical to enable both ways for that case, as well. Just a special condition to be added for SIB with two different Regs with no Scale, and one of the regs being esp...


Betov.

Yes, FASM allows exchange index and base registers - it is equal to write
[esi+4*edi] or [4*edi+esi]. But in the case of esp, there is special case, so I think it can be considered as "minor bug" and probably Privalov will fix it very quick.

Regards.

Oh, i wouldn't even say "a minor bug" This just requires a special case consideration for full flexibility... well...


Betov.

The problem is that [esp+ebx] uses by default stack segment
while [ebx+esp] is suposed to use data segment.
if fasm swap registers the programmer could think erroneously that he is
using data segment instead of stack segment.
Of course, for flat memory model this is not important but fasm is a generic assembler. Only [ebp+esp] can be exchanged because both registers use stack segment by default, but i don´t consider this a bug,
and some times is better than the assembler shows to the programmer
that this instruction does not exist instead of arrange the code.

I agree with Octavio's point of view.

I agree with Ocatvio, privalov better document ths feature

Oh, Yes.


Betov.

[quote="Betov"]Oh, Yes.
quote]
M3 too