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flat assembler > Main > Database listing in which CPU instruction first appeared?

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zhak



Joined: 12 Apr 2005
Posts: 468
Location: Belarus
Database listing in which CPU instruction first appeared?
Sometimes I'm having hard time figuring out in what processor a particular instruction first appeared (talking about IA-32 / Intel 64 / AMD64). Intel Manual doesn't provide this info most of the time, so I'm just surfing Internet in search of any mentions.

For example, I discovered that MOVBE is Atom-specific instruction completely accidentally, browsing questions on StackOverflow. So, maybe there's some resource which I'm not aware of, like https://courses.engr.illinois.edu/ece390/resources/opcodes.html but a more complete one?
Post 02 May 2017, 19:12
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triplefault



Joined: 28 Mar 2012
Posts: 9
While I don't know about a list as organized as the one you posted I think the GCC manuals may have some of the information you are looking for. They have a list of CPU types and the instruction subsets supported by each of them. However, they only list instruction subsets so if you want to know when a particular instruction appeared you'll have to know to which instruction subset it belongs.

https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
Post 02 May 2017, 22:43
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rugxulo



Joined: 09 Aug 2005
Posts: 2109
Location: Usono (aka, USA)
Are you just curious? It doesn't practically matter when/where it was first supported, rather only if/whether your current target cpu supports it (e.g. check CPUID at runtime, branch accordingly).

But see NASM -- Appendix B : Instruction List. E.g. it says "MOVBE" was "NEHALEM", "CLMUL" was "WESTMERE", etc.
Post 08 May 2017, 13:42
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zhak



Joined: 12 Apr 2005
Posts: 468
Location: Belarus
Well, it contradicts to what's stated on Intel site: https://software.intel.com/en-us/articles/disable-movbe-to-test-intel-atom-targeted-code-on-non-atom-platforms/


Quote:

The Intel® Compilers 11.0 allow you to target the Intel® Atom™ processor using the /QxSSE3_ATOM or -xSSE3_ATOM compiler options. These options enable the generation of the movbe instruction which is unique to the Intel® Atom™ processor. However, there is sometimes a need to run such codes on a different processor such as the Intel® Pentium® III processor (for example, for validation purposes where an Intel® Atom™ processor isn't available). In these situations, the compiler provides the /Qinstruction:nomovbe (for Windows*) and -minstruction=nomovbe (for Linux*/Mac*) options to disable the generation of this instruction.



So' I'd expect it to be bonnell, not nehalem.

Apart from curiosity, I'm creating a framework for my future project based on fasmg engine. As one of the features it should allow selecting target cpu with a set of default options. But I don't want to take some list from nasm or gcc or whatever and blindly follow it. I just want to know exactly what I'm doing, so I have to gather information by crumbs and check and re-check it over and over again %)
Post 08 May 2017, 14:48
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VEG



Joined: 06 Feb 2013
Posts: 51
Location: Minsk, Belarus

Quote:
I discovered that MOVBE is Atom-specific instruction

I've googled a little bit about it, and it seems that it is not true.

https://en.wikipedia.org/wiki/Jaguar_%28microarchitecture%29


Quote:
The Jaguar core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.

So, AMD also supports.

https://arstechnica.com/gadgets/2013/05/a-look-at-haswell/


Quote:
As an aside, Haswell adds a big-endian move instruction (MOVBE) that can convert to and from traditional x86 little-endian format (big-endian data stores the most significant byte first, while little endian stores the least significant byte first). This was originally introduced in Atom, and it was added to ensure full compatibility and improve performance for embedded applications.

A note from Intel itself:

https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family


Quote:
The 4th generation Intel® Core™ processor family (codenamed Haswell) introduces support for many new instructions that are specifically designed to provide better performance to a broad range of applications such as: media, gaming, data processing, hashing, cryptography, etc. The new instructions can be divided into the following categories:

Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Fused Multiply Add (FMA)
Bit Manipulation New Instructions (BMI)
MOVBE instruction (previously supported by the Intel® Atom™ processor)
Intel® Transactional Synchronization Extensions (Intel® TSX) (available in some models)

So, Haswell and newer processors from Intel support this instruction.

And it seems that FASMG doesn't support this instruction Smile
Post 08 May 2017, 21:28
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Tomasz Grysztar
Assembly Artist


Joined: 16 Jun 2003
Posts: 6310
Location: Kraków, Poland

VEG wrote:
And it seems that FASMG doesn't support this instruction Smile

FASMG by itself does not support any instructions at all. As for the availability of various x86 instruction sets in form of macros, see the other thread.
Post 08 May 2017, 22:02
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zhak



Joined: 12 Apr 2005
Posts: 468
Location: Belarus

Quote:

I've googled a little bit


This is some useful info. thanks, VEG Smile
Post 08 May 2017, 23:23
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