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flat assembler > Non-x86 architectures > [ARM] X86 Conversion: LEA R,[S*I+B+D], SETCC, XCHG, etc

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m3ntal



Joined: 08 Dec 2013
Posts: 296
Another attempt to convert X86 instructions to ARM. Example:
Code:
lea r1, [r2]
lea r1, [r2+r3]
lea r1, [r2+10000000h]
lea r1, [r2-20000000h]
lea r1, [r2*3]
lea r1, [r2*4]
lea r1, [r2*5]
lea r1, [r2*10]
lea r1, [r2+r3*4]
lea r1, [r4+r7*2+30000000h]
lea r2, 40000000h
lea r3, [50000000h]
lea r4, [60000000h+r7]
lea r5, [70000000h+r7*8]    
This generates the following ARM disassembly:
Code:
00000000 E1A01002 mov r1, r2
00000004 E0821003 add r1, r2, r3
00000008 E2821201 add r1, r2, 10000000h
0000000C E2421202 sub r1, r2, 20000000h
00000010 E0821082 add r1, r2, r2, lsl 1
00000014 E1A01102 mov r1, r2, lsl 2
00000018 E0821102 add r1, r2, r2, lsl 2
0000001C E0821102 add r1, r2, r2, lsl 2
00000020 E0811001 add r1, r1, r1
00000024 E0821103 add r1, r2, r3, lsl 2
00000028 E0841087 add r1, r4, r7, lsl 1
0000002C E2811203 add r1, r1, 30000000h
00000030 E3A02101 mov r2, 40000000h
00000034 E3A03205 mov r3, 50000000h
00000038 E2874206 add r4, r7, 60000000h
0000003C E3A05207 mov r5, 70000000h
00000040 E0855187 add r5, r5, r7, lsl 3    
LEA macro:
Code:
macro lea [p] {
 common
  define ?s 0
  match r=,[x], p \{         ; r,[?]
   if x is.r32?              ; r,[r]
    mov r, x
   else                      ; r,[?]
    match =0 \
     a+b*c, ?s x \\{
     match n+i, c \\\{       ; a+b*c+i
      addms r, a, b, n
      if use.ror?
       add r, i
      else
       ldr r12, =i
       add r, a, r12
      end if
      define ?s 1
     \\\}
     if ?s eq 0
      if a is.r32? \         ; r+r*c
       & b is.r32?
       addms r, a, b, c
      else if b is.r32? \    ; i+r*c
       & a is.i?
       if use.ror.a?
        mov r, a
        addms r, r, b, c
       else
        ldr r12, =i
        add r, a, r12
       end if
      else
       'Error'
      end if
     end if
     define ?s 1
    \\}
    match =0 \
     a+b, ?s x \\{
     if a is.r32? \          ; r+i
      & b is.i?
      if use.ror.b?
       add r, a, b
      else
       ldr r, =b
       add r, a, r
      end if
     else if \
      b is.r32? & \          ; i+r
      a is.i?
      if use.ror.a?
       add r, b, a
      else
       ldr r, =a
       add r, b, r
      end if
     else                    ; assume
      add r, a, b            ; r=a+b
     end if
     define ?s 1
    \\}
    match =0 \
     a-b, ?s x \\{           ; r-i
     if a is.r32? \
      & b is.i?
      if use.ror.b?
       sub r, a, b
      else
       ldr r, =b
       sub r, a, r
      end if
     else                    ; ?,?
      'Error'
     end if
     define ?s 1
    \\}
    match =0 \
     a*b, ?s x \\{           ; r=a*n
     if b eq 4
      mov r, a, lsl 2        ; r=a*4
     else if b eq 2
      mov r, a, lsl 1        ; r=a*2
     else if b eq 3
      add r, a, a, lsl 1     ; r=a*3
     else if b eq 5
      add r, a, a, lsl 2     ; r=a*5
     else if b eq 10
      add r, a, a, lsl 2     ; r=a*10
      add r, r
     else                    ; *?
      'Error'
     end if
     define ?s 1
    \\}
    if ?s eq 0               ; r=[i]
     ldr r, =x
    end if
   end if
   define ?s 1
  \}
  match =0 \                 ; no []
   a=,b, ?s p \{
   if a is.r32?              ; r,?
    if b is.r32?             ; r,r
     mov a, b
    else if b is.i?          ; r,i
     ldr a, =b
    else                     ; r,?
     'Error'
    end if
   else                      ; ?,?
    'Error'
   end if
   define ?s 1
  \}
  if ?s eq 0
   'Error'
  end if
}    
Attached is 3 examples. INTEL.INC converts X86 instructions to ARM: LEA, MOV/SX/ZX, ADD/SUB/ETC, BSWAP, XCHG, SETCC, BT/R/S, REP LODS/STOS/ETC.


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Post 15 Jul 2014, 20:58
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m3ntal



Joined: 08 Dec 2013
Posts: 296
XCHG and SETCC (INTEL.INC)
Code:
;;;;;;;;;;;;;;;;;;;; EXCHANGE ;;;;;;;;;;;;;;;;;;;;

; xchg r1, r2
; xchg r1, [r2+1000h]
; xchg r1, [r2+r3*4]
; xchg [r1+r2*8], r3

macro xchg a, b {
 define ?s 0
 match [m], a \{   ; [a], b
  mov r10, [m]
  mov [m], b
  mov b, r10
  define ?s 1
 \}
 match =0 \
  [m], ?s b \{     ; a, [b]
  mov r10, a
  mov a, [m]
  mov [m], r10
  define ?s 1
 \}
 if ?s eq 0
  if a is.r32? \   ; r, r
   & b is.r32?
   mov r10, a
   mov a, b
   mov b, r10
  else
   'Error'
  end if
 end if
}

;;;;;;;;;;;;;;;;;;;;;; SETCC ;;;;;;;;;;;;;;;;;;;;;

; set on condition

; sete cl
; setne dh
; setg [r0+r1*4]

macro setcc c, x {
 local n
 define ?s 0
 n=-1
 if x in <al,ah>
  n=0
 else if x in <cl,ch>
  n=1
 else if x in <dl,dh>
  n=2
 else if x in <bl,bh>
  n=3
 else
  match [m], x \{      ; [m8]
   mov r10, 0
   mov#c r10, 1
   lea r11, [m]
   strb r10, [r11]
   define ?s 1
  \}
 end if
 if ?s eq 0            ; register
  if n=-1
   'Error'
  end if
  if x in \            ; low 8BIT
   <al,cl,dl,bl>
   dw \                ; bic r, 0FFh
    (0E3C000FFh) or \
    (n shl 16) or \
    (n shl 12)
   dw \                ; orr#c r, 1
    (c.#c shl 28) or \
    (03800001h) or \
    (n shl 16) or \
    (n shl 12)
  else if x in \       ; high 8BIT
   <ah,ch,dh,bh>
   dw \                ; bic r, 0FF00h
    (0E3C00CFFh) or \
    (n shl 16) or \
    (n shl 12)
   dw \                ; orr#c r, 0100h
    (c.#c shl 28) or \
    (03800C01h) or \
    (n shl 16) or \
    (n shl 12)
  else
   'Error'
  end if
 end if
}

macro sete x { setcc eq, x }  ; equality
macro setz x { setcc eq, x }
macro setne x { setcc ne, x }
macro setnz x { setcc ne, x }

macro setc x { setcc hs, x }
macro setnc x { setcc lo, x }

macro seta x { setcc hi, x }  ; unsigned <>
macro setae x { setcc hs, x }
macro setb x { setcc lo, x }
macro setbe x { setcc ls, x }

macro setg x { setcc gt, x }  ; signed <>
macro setge x { setcc ge, x }
macro setl x { setcc lt, x }
macro setle x { setcc le, x }    
Post 15 Jul 2014, 21:17
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