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flat assembler > Non-x86 architectures > [fasmarm] CPU capability 5T

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Asvald



Joined: 11 Jun 2014
Posts: 2
[fasmarm] CPU capability 5T
Hi dudes! Can you ask me, why i can't compile this code for CPU_CAPABILITY_V5T (if uncomment processor 1 shl 09), but for CPU_CAPABILITY_V4T code is compiled perfectly. And how can i do it in fasm for 5T?
Error: Requires CPU capability 7M, use directive "processor" to select.


Code:
 format ELF executable
        entry start
        segment readable executable

       code16
       processor 1 shl 07       ;CPU_CAPABILITY_V4T
       ;processor 1 shl 09       ;CPU_CAPABILITY_V5T
start:
       LDRB    R0, [R6]
       LDR     R1, [R7,#4]
       ADDS    R6, #1
       STRB    R0, [R1]
       ADDS    R1, #1
       STR     R1, [R7,#4]

Post 11 Jun 2014, 08:05
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15233
Location: 1I/╩╗Oumuamua
You need to combine the capability bits. V5T only gives the extra V5T instructions provided, it does not enable all the previous version instructions.

So if your CPU can do all of V1 through to V5T but nothing higher then you should enable all of the V1 to V5T bits but not any others.
Post 11 Jun 2014, 08:33
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15233
Location: 1I/╩╗Oumuamua
Note that V5T only provides the following two instructions:
bkpt imm
blx reg

You can see this in the file "InstructionFormatsTHUMB16.asm". So things like ADD are not available without enabling the other instruction sets.
Post 11 Jun 2014, 08:38
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Asvald



Joined: 11 Jun 2014
Posts: 2
Thanks revolution! But can you explain me, why there is only blx reg, but what about "blx addr".
Post 11 Jun 2014, 11:22
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 15233
Location: 1I/╩╗Oumuamua
"blx offset" is available in V5 ARM mode and X capability THUMB mode. Have a look at the InstructionFormatsARM.asm and InstructionFormatsTHUMB32.asm files to see BLX used there.
Post 11 Jun 2014, 11:36
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