now, i think there is a stall there, for one of two reasons i cannot discriminate:
1) LDR is not listed at page 83 of manual V7M
2) whenever Flash-AHB on I-Code-bus of my STM32F4 can read 64 cache lines of 128 bits, the D-bus has priority on the on it, because fetching literals in the executable section.
reason 2) seems consequential but related. the stall explained in chap 3.3.2 Cortex-M4.
LDR Rx,[PC,#imm] might add 1 cycle because of contention with the fetch unit.
add then 2 cycles, because LDR using PC is a blocking operation. the fetch unit should be the one using the D-bus, while I-Bus already busy on a speculative read of the next 2,4 bytes in the code on "normal" memory.
one simpler solution, using MOVW+MOVT,
2 cycles using immediates, and it does not involve fetching from memory.
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