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flat assembler > Non-x86 architectures > [ARM] New .if.bit/s Syntax + Disassembler Preview

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uart777



Joined: 17 Jan 2012
Posts: 369
.if.bit/s compares BIT/s in the specified register or EAX. Syntax:

Code:
.if.bit 27, ecx
.if.bits 4-7=1001b
.if.bit 20, eax
.if.bits 31-24=11110011b    
.if.bit/s macros
Code:
macro syntax v {
 if v eq
  define ?s 1
 else
  define ?s v
 end if
}

macro verify e {
 if ?s eq 0
  display `e
  'Error: ' e
 end if
}

macro .if.bit n, r {
 if ~r eq
  mov edx, r
 else
  mov edx, eax
 end if
 local ..start, ..else, ..end
 ?IF equ
 ?START equ ..start
 ?ELSE equ ..else
 ?END equ ..end
 ?START:
 test edx, (1 shl n)
 jz ?ELSE
}

macro .if.not.bit n, r {
 if ~r eq
  mov edx, r
 else
  mov edx, eax
 end if
 local ..start, ..else, ..end
 ?IF equ
 ?START equ ..start
 ?ELSE equ ..else
 ?END equ ..end
 ?START:
 test edx, (1 shl n)
 jnz ?ELSE
}

; alters edx

macro .if.bits n, r {
 local i, b, lo, hi, mask
 syntax 0
 match l-h==v, n \{     ; BITs = value
  if l<h                ; low to high
   lo=l
   hi=h
  else                  ; high to low
   lo=h
   hi=l
  end if
  i=0                   ; search value from
  repeat 32             ; left to right (31-0)
   if v and \           ; for 1st BIT set...
    (1 shl (31-i))<>0
    break
   end if
   i=i+1
  end repeat
  b=0                   ; # BITs required
  repeat 32-i           ; for v/alue
   b=b+1
  end repeat
  if b>(hi-lo+1)        ; example: 4-5=111b
   'Value exceeds size' ; 4-5 is only 2BITs,
  end if                ; not enough for 111b.
  i=0
  mask=0                ; create mask: 111xb
  repeat (hi-lo+1)      ; # 1 BITs
   mask=\
    (mask or (1 shl i))
   i=i+1
  end repeat
  local ..start, ..else, ..end
  ?IF equ
  ?START equ ..start
  ?ELSE equ ..else
  ?END equ ..end
  if ~r eq
   mov edx, r
  else
   mov edx, eax
  end if
  shr edx, lo           ; extract BITs
  and edx, mask
  ?START:
  cmp edx, v
  jne ?ELSE
  syntax 1
 \}
 verify
}

macro .end {
 if ?IF eq
  ?ELSE:
 end if
 ?END:
 restore ?IF, ?START, ?ELSE, ?END
}    
D-ARM7

I'm working on an ARM disassembler and have used .if.bit/s to decode instructions. I had to manually extract, copy, edit, convert (calculator), compare BITs so many times (1,000s) that I decided to create a macro for it. Excerpts:
Code:
;               ___               ____
;              / _ \___ _______ _/_  /
;             / // / _ `/ __/  ' \/ /
;            /____/\_,_/_/ /_/_/_/_/

;            D-ARM7 Disassembler *Beta*...

 ; class 1: dual multiply, sxxt sign
 ; extend, load/store single word,
 ; us byte, etc...

 .1:
 .if.bits 25-20=110000b
   .if.bit 4
     .if.bits 7-6=0
       .if.bits 15-12=1111b
         .if.bit 5
           return I.SMUADX
         .end
         return I.SMUAD
       .end
       return I.SMLAD
     .end
     .if.bits 7-6=1
       .if.bits 15-12=1111b
         .if.bit 5
           return I.SMUSDX
         .end
         return I.SMUSD
       .end
       return I.SMLSD
     .end
   .end
 .end
 .if.bits 25-20=110100b
   .if.bits 7-6=1
     return I.SMLSLD
   .end
   return I.SMLALD
 .end   
 
 ; load/store signed byte, un/signed half
 ; or dual...

 .if.bits 27-25=0
   .if.bits 11-4=1011b
     .if.bit 20
       return I.LDRH   ; load half
     .end
     return I.STRH     ; store half
   .end
   .if.bits 11-4=1111b
     .if.bit 20
       return I.LDRSH  ; load signed half
     .end
     return I.STRD     ; store dual
   .end
   .if.bits 11-4=1101b
     .if.bit 20
       return I.LDRSB  ; load signed byte
     .end
     return I.LDRD     ; load dual
   .end
 .end

 .if.bits 9-4=000111b
   .if.bits 25-20=101010b
     .if.bits 19-16=1111b
       return I.SXTB
     .end
     return I.SXTAB
   .end
   .if.bits 25-20=101000b
     .if.bits 19-16=1111b
       return I.SXTB16
     .end
     return I.SXTAB16
   .end
   .if.bits 25-20=101011b
     .if.bits 19-16=1111b
       return I.SXTH
     .end
     return I.SXTAH
   .end
   .if.bits 25-20=101110b
     .if.bits 19-16=1111b
       return I.UXTB
     .end
     return I.UXTAB
   .end
   .if.bits 25-20=101111b
     .if.bits 19-16=1111b
       return I.UXTH
     .end
     return I.UXTAH
   .end
   .if.bits 25-20=101100b
     .if.bits 19-16=1111b
       return I.UXTB16
     .end
     return I.UXTAB16
   .end
 .end

 .if.bits 5-4=01b
   .if.bits 25-21=10101b
     return I.SSAT
   .end
   .if.bits 25-21=10111b
     return I.USAT
   .end
 .end
 .if.bits 25-20=101010b
   .if.bits 11-4=11110011b
     return I.SSAT16
   .end
 .end
 .if.bits 25-20=101110b
   .if.bits 11-4=11110011b
     return I.USAT16
   .end
 .end

 .if.bits 25-20=100001b
   .if.bits 11-8=1111b
     .if.bits 7-4=1001b
       return I.SADD8
     .end
     .if.bits 7-4=0001b
       return I.SADD16
     .end
     .if.bits 7-4=1111b
       return I.SSUB8
     .end
     .if.bits 7-4=0111b
       return I.SSUB16
     .end
     .if.bits 7-4=0011b
       return I.SASX
     .end
     .if.bits 7-4=0101b
       return I.SSAX
     .end
   .end
 .end

 .if.bits 25-20=100101b
   .if.bits 11-8=1111b
     .if.bits 7-4=1001b
       return I.UADD8
     .end
     .if.bits 7-4=0001b
       return I.UADD16
     .end
     .if.bits 7-4=1111b
       return I.USUB8
     .end
     .if.bits 7-4=0111b
       return I.USUB16
     .end
     .if.bits 7-4=0011b
       return I.UASX
     .end
     .if.bits 7-4=0101b
       return I.USAX
     .end
   .end
 .end

 .if.bits 25-20=100011b
   .if.bits 11-8=1111b
     .if.bits 7-4=1001b
       return I.SHADD8
     .end
     .if.bits 7-4=0001b
       return I.SHADD16
     .end
     .if.bits 7-4=1111b
       return I.SHSUB8
     .end
     .if.bits 7-4=0111b
       return I.SHSUB16
     .end
     .if.bits 7-4=0011b
       return I.SHASX
     .end
     .if.bits 7-4=0101b
       return I.SHSAX
     .end
   .end
 .end

 .if.bits 25-20=100111b
   .if.bits 11-8=1111b
     .if.bits 7-4=1001b
       return I.UHADD8
     .end
     .if.bits 7-4=0001b
       return I.UHADD16
     .end
     .if.bits 7-4=1111b
       return I.UHSUB8
     .end
     .if.bits 7-4=0111b
       return I.UHSUB16
     .end
     .if.bits 7-4=0011b
       return I.UHASX
     .end
     .if.bits 7-4=0101b
       return I.UHSAX
     .end
   .end
 .end

 .if.bits 25-20=111000b
   .if.bits 7-4=1
     .if.bits 15-12=1111b
       return I.USAD8
     .end
     return I.USADA8
   .end
 .end

 .if.bits 25-20=100010b
   .if.bits 11-8=1111b
     .if.bits 7-4=0011b
       return I.QASX
     .end
     .if.bits 7-4=0101b
       return I.QSAX
     .end
     .if.bits 7-4=1001b
       return I.QADD8
     .end
     .if.bits 7-4=0001b
       return I.QADD16
     .end
     .if.bits 7-4=1111b
       return I.QSUB8
     .end
     .if.bits 7-4=0111b
       return I.QSUB16
     .end
   .end
 .end

 .if.bits 25-20=100110b
   .if.bits 11-8=1111b
     .if.bits 7-4=0011b
       return I.UQASX
     .end
     .if.bits 7-4=0101b
       return I.UQSAX
     .end
     .if.bits 7-4=1001b
       return I.UQADD8
     .end
      .if.bits 7-4=0001b
       return I.UQADD16
     .end
     .if.bits 7-4=1111b
       return I.UQSUB8
     .end
      .if.bits 7-4=0111b
       return I.UQSUB16
     .end
   .end
 .end

 .if.bits 25-20=101000b
   .if.bits 5-4=01b
     .if.bit 6
       return I.PKHTB
     .end
     return I.PKHBT
   .end
 .end

 .if.bits 25-16=1010111111b
   .if.bits 11-8=1111b
     .if.bits 7-4=0011b
       return I.REV
     .end
     .if.bits 7-4=1011b
       return I.REV16
     .end
   .end
 .end

 .if.bits 25-16=1011111111b
   .if.bits 11-8=1111b
     .if.bits 7-4=1011b
       return I.REVSH
     .end
     .if.bits 7-4=0011b
       return I.RBIT
     .end
   .end
 .end

 .if.bits 25-21=11110b
   .if.bits 6-4=1
     .if.bits 3-0=1111b
       return I.BFC
     .end
     return I.BFI
   .end
 .end

 ; class 3: co-processor instructions...

 .3:
 .if eax=-1                  ; assume -1
   return I.DATA             ; is data
 .end
 .if.bits 25-24=11b          ; swi/svc #
   return I.SWI
 .end
 .if.bits 25-24=10b         
   .if.not.bit 20            ; mcr/2
     .if.bit 4
       .if.bits 31-28=1111b
         return I.MCR2
       .end
       return I.MCR
     .end
   .else                     ; mrc/2
     .if.bit 4
       .if.bits 31-28=1111b
         return I.MRC2
       .end
       return I.MRC
     .end
   .end
   .if.not.bit 4             ; cdp/2 data
     .if.bits 31-28=1111b    ; operation
       return I.CDP2
     .end
     return I.CDP
   .end
 .end
 .if.bits 25-20=101b         ; mrrc/2
   .if.bits 31-28=1111b
     return I.MRRC2
   .end
   return I.MRRC
 .end
 .if.bits 25-20=000100b      ; mcrr/2
   .if.bits 31-28=1111b
     return I.MCRR2
   .end
   return I.MCRR
 .end

 .if.not.bit 25              ; ldcx, stcx
   .if.bits 31-28=1111b      ; co-processor
     .if.bit 20              ; data transfer
       .if.bit 22
         return I.LDC2L
       .end
       return I.LDC2
     .end
     .if.bit 22
       return I.STC2L
     .end
     return I.STC2
   .end
   .if.bit 20
     .if.bit 22
       return I.LDCL
     .end
     return I.LDC
   .end
   .if.bit 22
     return I.STCL
   .end
   return I.STC
 .end    

.if.bit/s has super-charged my production speed. Within 2 days of using it, D-ARM7 now recognizes ARM (A1), FP and some advanced SIMD/VFP. When finished, will post in Non-X86.
Post 28 Sep 2013, 15:22
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dogman



Joined: 18 Jul 2013
Posts: 114
Have you seen Randy Hyde's HLASM? It seems to have a lot of stuff you would like although it doesn't run on ARM and the 64 bit Intel stuff hasn't been released.
Post 29 Sep 2013, 06:05
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HaHaAnonymous



Joined: 02 Dec 2012
Posts: 1181
Location: Unknown
Stupid post removed.


Last edited by HaHaAnonymous on 28 Feb 2015, 19:48; edited 1 time in total
Post 29 Sep 2013, 15:26
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uart777



Joined: 17 Jan 2012
Posts: 369
Quote:
Have you seen Randy Hyde's HLASM? It seems to have a lot of stuff you would like
Yes, a long time ago. I like Randall Hyde and his tutorials but I do NOT like HLA or RosASM. IMO, they are failed attempts at creating a hybrid assembler/compiler and no one has created any significant programs with them. By the way, I don't come here asking for help or advice.

D-ARM7 INSTRUCTIONS
Code:
; ids and names. 370+ instructions (or 7,000+
; considering conditions/suffixes/variations and
; that's a low estimate) 

 MESSAGES i.names.ta,\
 I.UNKNOWN='?', I.DATA='dw',\
 I.ABS='abs%', I.ACS='acs%', I.ADC='adc$',\
 I.ADD='add$', I.ADF='adf%', I.AND='and$',\
 I.ASN='asn%', I.ASR='asr$', I.ATN='atn%',\
 I.B='b?', I.BFC='bfc?', I.BFI='bfi?',\
 I.BIC='bic$', I.BKPT='bkpt?', I.BL='bl?',\
 I.BLX='blx?', I.BX='bx?', I.BXJ='bxj?',\
 I.CDP='cdp', I.CDP2='cdp2', CLREX='clrex',\
 I.CLZ='clz?', I.CMN='cmn$', I.CMF='cmf?',\
 I.CMP='cmp$', I.CNF='cnf?', I.COS='cos%',\
 I.CPS='cps', I.DBG='dbg?', I.DMB='dmb',\
 I.DSB='dsb', I.DVF='dvf%', I.EOR='eor$',\
 I.EXP='exp%', I.FDV='fdv%', I.FIX='fix%',\
 I.FLT='flt%', I.FML='fml%', I.FRD='frd%',\
 I.ISB='isb?', I.LDC='ldc?', I.LDC2='ldc2',\
 I.LDCL='ldcl?', I.LDC2L='ldc2l',\
 I.LDF='ldf.', I.LDMEA='ldmea?',\
 I.LDMED='ldmed?', I.LDMFA='ldmfa?',\
 I.LDMFD='ldmfd?', I.LDR='ldr?',\
 I.LDRB='ldrb?', I.LDRD='ldrd?',\
 I.LDREX='ldrex?', I.LDREXB='ldrexb?',\
 I.LDREXD='ldrexd?', I.LDREXH='ldrexh?',\
 I.LDRH='ldrh?', I.LDRSB='ldrsb?',\
 I.LDRSH='ldrsh?', I.LFMEA='lfmea?',\
 I.LFMED='lfmed?', I.LFMFA='lfmfa?',\
 I.LFMFD='lfmfd?', I.LGN='lgn%', I.LOG='log%',\
 I.LSL='lsl$', I.LSR='lsr$', I.MAR='mar?',\
 I.MCR='mcr?', I.MCR2='mcr2', I.MCRR='mcrr?',\
 I.MCRR2='mcrr2', I.MLA='mla$', I.MLS='mls$',\
 I.MNF='mnf%', I.MOV='mov$', I.MOVT='movt?',\
 I.MOVW='movw?', I.MRA='mra?', I.MRC='mrc?',\
 I.MRC2='mrc2', I.MRRC='mrrc?',\
 I.MRRC2='mrrc2', I.MRS='mrs?', I.MSR='msr?',\
 I.MUF='muf%', I.MUL='mul$', I.MULL='mull$',\
 I.MVF='mvf%', I.MVN='mvn$', I.NOP='nop',\
 I.NRM='nrm%', I.ORR='orr$', I.PKHBT='pkhbt?',\
 I.PKHTB='pkhtb?', I.PLD='pld', I.PLDW='pldw',\
 I.PLI='pli', I.POL='pol%', I.POW='pow%',\
 I.QADD='qadd?', I.QADD16='qadd16?',\
 I.QADD8='qadd8?', I.QASX='qasx?',\
 I.QDADD='qdadd?', I.QDSUB='qdsub?',\
 I.QSAX='qsax?', I.QSUB='qsub?',\
 I.QSUB16='qsub16?', I.QSUB8='qsub8?',\
 I.RBIT='rbit?', I.RDF='rdf%', I.REV='rev?',\
 I.REV16='rev16?', I.REVSH='revsh?',\
 I.RFC='rfc?', I.RFE='rfe', I.RFS='rfs?',\
 I.RMF='rmf%', I.RND='rnd%', I.ROR='ror$',\
 I.RPW='rpw%', I.RRX='rrx?', I.RSB='rsb$',\
 I.RSC='rsc$', I.RSF='rsf%', I.SADD16='sadd16?',\
 I.SADD8='sadd8?', I.SASX='sasx?', I.SBC='sbc$',\
 I.SBFX='sbfx?', I.SDIV='sdiv?',\
 I.SETEND='setend', I.SEV='sev?',\
 I.SFMEA='sfmea?', I.SFMED='sfmed?',\
 I.SFMFA='sfmfa?', I.SFMFD='sfmfd?',\
 I.SHADD16='shadd16?', I.SHADD8='shadd8?',\
 I.SHASX='shasx?', I.SHSAX='shsax?',\
 I.SHSUB16='shsub16?', I.SHSUB8='shsub8?',\
 I.SIN='sin%', I.SMC='smc?',\
 I.SMLABB='smlabb?', I.SMLABT='smlabt?',\
 I.SMLAD='smlad?', I.SMLAL='smlal$',\
 I.SMLALBB='smlalbb?', I.SMLALBT='smlalbt?',\
 I.SMLALD='smlald?', I.SMLALTB='smlaltb?',\
 I.SMLALTT='smlaltt?', I.SMLATB='smlatb?',\
 I.SMLATT='smlatt?', I.SMLAWB='smlawb?',\
 I.SMLAWT='smlawt?', I.SMLSD='smlsd?',\
 I.SMLSLD='smlsld?', I.SMUAD='smuad?',\
 I.SMUADX='smuadx?', I.SMULBB='smulbb?',\
 I.SMULBT='smulbt?', I.SMULL='smull$',\
 I.SMULTB='smultb?', I.SMULTT='smultt?',\
 I.SMULWB='smulwb?', I.SMULWT='smulwt?',\
 I.SMUSD='smusd?', I.SMUSDX='smusdx?',\
 I.SQT='sqt%', I.SRS='srs', I.SSAT='ssat?',\
 I.SSAT16='ssat16?', I.SSAX='ssax?',\
 I.SSUB8='ssub8?', I.SSUB16='ssub16?',\
 I.STC='stc?', I.STC2='stc2', I.STCL='stcl?',\
 I.STC2L='stc2l', I.STF='stf.',\
 I.STMEA='stmea?', I.STMED='stmed?',\
 I.STMFA='stmfa?', I.STMFD='stmfd?',\
 I.STR='str?', I.STRB='strb?', I.STRD='strd?',\
 I.STREX='strex?', I.STREXB='strexb?',\
 I.STREXD='strexd?', I.STREXH='strexh?',\
 I.STRH='strh?', I.SUB='sub$', I.SUF='suf%',\
 I.SWI='swi?', I.SWP='swp?', I.SWPB='swpb?',\
 I.SXTAB='sxtab?', I.SXTAH='sxtah?',\
 I.SXTAB16='sxtab16?', I.SXTB='sxtb?',\
 I.SXTB16='sxtb16?', I.SXTH='sxth?',\
 I.TAN='tan%', I.TEQ='teq$', I.TST='tst$',\
 I.UADD16='uadd16?', I.UADD8='uadd8?',\
 I.UASX='uasx?', I.UBFX='ubfx?', I.UDIV='udiv?',\
 I.UHADD16='uhadd16?', I.UHADD8='uhadd8?',\
 I.UHASX='uhasx?', I.UHSAX='uhsax?',\
 I.UHSUB16='uhsub16?', I.UHSUB8='uhsub8?',\
 I.UMAAL='umaal$', I.UMLAL='umlal$',\
 I.UMULL='umull$', I.UQADD16='uqadd16?',\
 I.UQADD8='uqadd8?', I.UQASX='uqasx?',\
 I.UQSAX='uqsax?', I.UQSUB16='uqsub16?',\
 I.UQSUB8='uqsub8?', I.URD='urd%',\
 I.USAD8='usad8?', I.USADA8='usada8?',\
 I.USAT='usat?', I.USAT16='usat16?',\
 I.USAX='usax?', I.USUB16='usub16?',\
 I.USUB8='usub8?', I.UXTAB='uxtab?',\
 I.UXTAB16='uxtab16?', I.UXTAH='uxtah?',\
 I.UXTB='uxtb?', I.UXTB16='uxtb16?',\
 I.UXTH='uxth?', I.VABA='vaba',\
 I.VABAL='vabal', I.VABD='vabd',\
 I.VABDL='vabdl', I.VABS='vabs',\
 I.VACGE='vacge', I.VACGT='vacgt',\
 I.VACLE='vacle', I.VACLT='vaclt',\
 I.VADD='vadd', I.VADDHN='vaddhn',\
 I.VADDL='vaddl', I.VADDW='vaddw',\
 I.VAND='vand', I.VBIC='vbic', I.VBIF='vbif',\
 I.VBIT='vbit', I.VBSL='vbsl',\
 I.VCEQ='vceq', I.VCGE='vcge',\
 I.VCGT='vcgt', I.VCLE='vcle', I.VCLS='vcls',\
 I.VCLT='vclt', I.VCLZ='vclz', I.VCMP='vcmp',\
 I.VCMPE='vcmpe', I.VCNT='vcnt',\
 I.VCVT='vcvt', I.VCVTB='vcvtb',\
 I.VCVTR='vcvtr', I.VCVTT='vcvtt',\
 I.VDIV='vdiv', I.VDUP='vdup', I.VEOR='veor',\
 I.VFMA='vfma', I.VFMS='vfms', I.VFNMA='vfnma',\
 I.VFNMS='vfnms', I.VHADD='vhadd',\
 I.VHSUB='vhsub', I.VLD1='vld1',\
 I.VLD2='vld2', I.VLD3='vld3', I.VLD4='vld4',\
 I.VLDMIA='vldmia', I.VLDMDB='vldmdb',\
 I.VLDR='vldr', I.VMAX='vmax', I.VMIN='vmin',\
 I.VMLA='vmla', I.VMLAL='vmlal',\
 I.VMLS='vmls', I.VMLSL='vmlsl', I.VMOV='vmov',\
 I.VMOVL='vmovl', I.VMOVN='vmovn', I.VMRS='vmrs',\
 I.VMSR='vmsr', I.VMUL='vmul', I.VMULL='vmull',\
 I.VMVN='vmvn', I.VNEG='vneg', I.VNMLA='vnmla',\
 I.VNMLS='vnmls', I.VNMUL='vnmul',\
 I.VORR='vorr', I.VORN='vorn', I.VPADAL='vpadal',\
 I.VPADD='vpadd', I.VPADDL='vpaddl',\
 I.VPMAX='vpmax', I.VPMIN='vpmin', I.VPOP='vpop',\
 I.VPUSH='vpush', I.VQABS='vqabs',\
 I.VQADD='vqadd', I.VQDMLAL='vqdmlal',\
 I.VQDMLSL='vqdmlsl', I.VQDMULH='vqdmulh',\
 I.VQDMULL='vqdmull', I.VQMOVN='vqmovn',\
 I.VQMOVUN='vqmovun', I.VQRDMULH='vqrdmulh',\
 I.VQRSHL='vqrshl', I.VQNEG='vqneg',\
 I.VQSHL='vqshl', I.VQSHLU='vqshlu',\
 I.VQSHRN='vqshrn', I.VQSHRUN='vqshrun',\
 I.VQSUB='vqsub', I.VQRSHRN='vqrshrn',\
 I.VQRSHRUN='vqrshrun', I.VRADDHN='vraddhn',\
 I.VRECPE='vrecpe', I.VRECPS='vrecps',\
 I.VREV16='vrev16', I.VREV32='vrev32',\
 I.VREV64='vrev64', I.VRHADD='vrhadd',\
 I.VRSHL='vrshl', I.VRSHR='vrshr',\
 I.VRSHRN='vrshrn', I.VRSRA='vrsra',\
 I.VRSQRTE='vrsqrte', I.VRSQRTS='vrsqrts',\
 I.VRSUBHN='vrsubhn', I.VSHL='vshl',\
 I.VSHLL='vshll', I.VSHR='vshr',\
 I.VSHRN='vshrn', I.VSLI='vsli',\
 I.VSQRT='vsqrt', I.VSRA='vsra', I.VSRI='vsri',\
 I.VST1='vst1', I.VST2='vst2', I.VST3='vst3',\
 I.VST4='vst4', I.VSTMIA='vstmia',\
 I.VSTMDB='vstmdb', I.VSTR='vstr',\
 I.VSUB='vsub', I.VSUBHN='vsubhn',\
 I.VSUBL='vsubl', I.VSUBW='vsubw', I.VSWP='vswp',\
 I.VTRN='vtrn', I.VTST='vtst',\
 I.VUZP='vuzp', I.VZIP='vzip',\
 I.WFC='wfc?', I.WFE='wfe?', I.WFI='wfi?',\
 I.WFS='wfs?', I.YIELD='yield?'    
Preview of VFP (Vector Floating Point) decoding using .if.bit/s (Beta, testing)

Excerpts from function identify(instruction). It determines the instruction type and returns I.* (I.ADD, I.SUB, etc). Index can be associated with a description or help file with encodings and examples (\HELP\mov.txt, ldr.txt, eor.txt) or a common parameter format (RD.RM.ETC).
Code:
.if.bits 31-25=1111001b
   .if.not.bit 23
     .if.bits 11-8=0
       .if.bit 9
         return I.VHSUB
       .end
       return I.VHADD
     .end
     .if.bits 11-8=1
       .if.not.bit 4
         return I.VRHADD
       .end
       let ecx=eax,\
        ecx>>>20, ecx&11b
       .if.not.bit 24
         .if ecx=0
           return I.VAND
         .end
         .if ecx=1
           return I.VBIC
         .end
         .if ecx=2
           return I.VORR
         .end
         .if ecx=3
           return I.VORN
         .end
       .else
         .if ecx=0
           return I.VEOR
         .end
         .if ecx=1
           return I.VBSL
         .end
         .if ecx=2
           return I.VBIT
         .end
         .if ecx=3
           return I.VBIF
         .end
       .end
     .end
     .if.bits 11-8=10b
       .if.not.bit 4
         .if.bit 9
           return I.VHSUB
         .end
         return I.VHADD
       .else
         return I.VQSUB
       .end
     .end
     .if.bits 11-8=11b
       .if.bit 4
         return I.VCGE
       .end
       return I.VCGT
     .end
     .if.bits 11-8=0100b
       .if.bit 4
         return I.VQSHL
       .end
       return I.VSHL
     .end
     .if.bits 11-8=0101b
       .if.bit 4
         return I.VQRSHL
       .end
       return I.VRSHL
     .end
     .if.bits 11-8=0110b
       .if.bit 4
         return I.VMAX
       .end
       return I.VMIN
     .end
     .if.bits 11-8=0111b
       .if.not.bit 4
         .if.not.bit 23
           return I.VABD
         .end
         return I.VABDL
       .end
       .if.not.bit 23
         return I.VABA
       .end
       return I.VABAL
     .end
     .if.bits 11-8=1000b
       .if.not.bit 4
         .if.bit 24
           return I.VADD
         .end
         return I.VSUB
       .else
         .if.not.bit 24
           return I.VTST
         .end
       .end
       return I.VCEQ
     .end
     .if.bits 11-8=1001b
       .if.not.bit 4
         .if.not.bit 9
           return I.VMLA
         .end
         return I.VMLS
       .end
       return I.VMUL
     .end
     .if.bits 11-8=1010b
       .if.not.bit 4
         return I.VPMAX
       .end
       return I.VPMIN
     .end
     .if.bits 11-8=1011b
       .if.not.bit 24
         .if.bit 4
           return I.VQRDMULH
         .end
         return I.VQDMULH
       .end
       return I.VPMIN
     .end
     .if.bits 11-8=1101b
       .if.not.bit 4
         .if.not.bit 24
           .if.bits 21-20=0
             return I.VADD
           .end
           return I.VSUB
         .end
         .if.bits 21-20=0
           return I.VPADD
         .end
         return I.VABD
       .end
       .if.not.bit 24
         .if.bit 4
           return I.VMLA
         .end
         return I.VMLS
       .end
       .if.bits 21-20=0
         return I.VMUL
       .end
     .end
     .if.bits 11-8=1110b
       .if.not.bit 4
         .if.not.bit 24
           return I.VCEQ
         .end
         .if.not.bit 21
           return I.VCGE
         .end
         return I.VCGT
       .else
         .if.bit 24
           .if.not.bit 21
             return I.VACGE
           .end
           return I.VACGT
         .end
       .end
     .end
     .if.bits 11-8=1111b
       .if.not.bit 4
         .if.not.bit 24
           .if.not.bit 21
             return I.VMAX
           .end
           return I.VMIN
         .end
         .if.not.bit 21
           return I.VPMAX
         .end
         return I.VPMIN
       .end
       .if.not.bit 24
         .if.not.bit 21
           return I.VRECPS
         .end
         return I.VRSQRTS
       .end
     .end
   .end    

Interface Ideas/Design/Settings
Code:
[#] DARM7 [File] +-
           > Recent _ Open _ Save .ASM _ Exit
[RL] [A] [C] [F] [CS] [R] [CF]
[P] [I>] [_] [HI] [CL]

+- Zoom In, Zoom Out
[RL] Reload/Re-Disassemble - F1/F9
     (After Editing/Assembly/Compile)
[A] View Addresses? Yes
[C] View Code? Yes
[F] Format: FASM (or GCC or Magic)
[CS] Case: Lower
[R] View registers: R0-R11 (or A1-V8)
[CF] Compact form? 2 operands
     for "DP A, A, B"? No
[P] Pseudo instructions?
    NOP/RET/ETC. Yes
[I>] Indent operands? Yes
[_] Space after commas? Yes
[HI] Highlight instructions?
     Clarify suffixes? No
[CL] Colors    
Post 30 Sep 2013, 13:27
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uart777



Joined: 17 Jan 2012
Posts: 369
VFP examples:
Code:
macro test.vfp {
 vaba.s32 d1, d2, d3
 vabal.s32 q1, d2, d3
 vabd.s32 q1, q2, q3
 vabdl.s32 q1, d2, d3
 vabs.f64 d1, d2
 vacge.f32 q1, q2
 vacgt.f32 q1, q2
 vacle.f32 q1, q2
 vaclt.f32 d1, d2
 vadd.f32 s1, s2, s3
 vaddhn.i32 d1, q2, q3
 vaddl.u32 q1, d2, d3
 vaddw.s32 q1, q2, d3
 vbic d1, d2, d3
 vbic q1, q2, q3
 vbit q1, q2, q3
 vbif q1, q2, q3
 vbsl q1, q2, q3
 vceq.f32 d1, d2, d3
 vcge.s32 d1, d2, d3
 vcgt.u16 d1, d2, d3
 vcle.s8 d1, d2, d3
 vcls.s32 d1, d2
 vclt.f32 q1, q2, q3
 vclz.i8 d1, d2
 vcmp.f32 s1, s2
 vcmpe.f64 d1, d2
 vcnt.8 d1, d2
 vcvt.s32.f32 d1, d2
 vcvtb.f16.f32 s1, s2
 vcvtr.u32.f64 s1, d2
 vcvtt.f32.f16 s1, s2
 vdiv.f64 d1, d2
 vdup.8 d1, r2
 vfma.f32 s1, s2, s3
 vfms.f32 d1, d2, d3
 vfnma.f32 s1, s2, s3
 vfnms.f64 d1, d2, d3
 vhadd.s32 d1, d2
 vhsub.u32 d1, d2
 vld1.64 \{d1,d2,d3,d4\}, [r0]!
 vld2.16 \{d0,d1\}, [r1], r2
 vld3.8 \{d0,d1,d2\}, [r1]!
 vld4.32 \{d6,d7,d8,d9\}, [r7], r4
 vldmia sp!, \{s0-s7\}
 vldmdb sp!, \{d0-d7\}
 vldr.32 s1, [r7]
 vldr.64 d1, [r7, 128]
 vmax.u32 d1, d2, d3
 vmin.s32 q1, q2, q3
 vmla.u32 d1, d2, d3
 vmla.s32 q1, q2, d0[1]
 vmlal.s32 q1, d2, d3
 vmlal.s32 q1, d2, d0[1]
 vmls.u8 q1, q2, q3
 vmls.s32 q1, q2, d0[1]
 vmlsl.s16 q1, d2, d3
 vmlsl.s32 q1, d2, d0[1]
 vmov d1, d2
 vmov q1, q2
 vmovl.u32 q1, d2
 vmovn.i32 d1, q2
 vmrs r0, fpscr
 vmsr fpscr, r1
 vmul.i32 d1, d2, d3
 vmull.u32 q1, d2, d3
 vmvn.i32 d1, 1
 vneg.f32 s1, s2
 vnmla.f32 s1, s2, s3
 vnmls.f64 d1, d2, d3
 vnmul.f32 s1, s2, s3
 vorr d1, d2
 vpadal.s32 d1, d2
 vpadd.f32 d1, d2
 vpaddl.s32 q1, q2
 vpmax.f32 d1, d2
 vpmin.f32 d1, d2
 vqabs.s8 d1, d2
 vqadd.s32 d1, d2
 vqdmlal.s32 q1, d2, d3
 vqdmlsl.s32 q1, d2, d0[1]
 vqdmulh.s32 d1, d2, d3
 vqdmull.s32 q1, d2, d3[0]
 vqmovn.u64 d1, q2
 vqmovun.s32 d1, q2
 vqrdmulh.s32 d1, d2
 vqneg.s8 d1, d2
 vqrshl.s32 d1, d2
 vqshl.s32 d1, d2
 vqshlu.s64 q1, q2, 63
 vqshrn.s64 d1, q2, 16
 vqshrun.s32 d1, q2, 12
 vqrshrn.s32 d1, q2, 8
 vqrshrun.s32 d1, q2, 4
 vqsub.s32 d1, d2
 vraddhn.i32 d1, q2, q3
 vrecpe.u32 d1, d2
 vrecps.f32 d1, d2
 vrev16.8 d1, d2
 vrev32.16 d1, d2
 vrev64.32 d1, d2
 vrhadd.s32 d1, d2
 vrshl.u64 d1, d2
 vrshr.u64 d1, d2, 56
 vrshrn.i64 d1, q2, 31
 vrsra.s32 d1, d2, 8
 vrsqrte.f32 d1, d2
 vrsqrts.f32 q1, q2
 vrsubhn.i64 d1, q2, q3
 vshl.s32 d1, d2
 vshll.u32 q1, d2, 4
 vshr.u64 q1, q2, 7
 vshrn.i64 d1, q2, 7
 vsli.32 d1, d2, 12
 vsqrt.f32 s1, s2
 vsra.u64 q1, q2, 27
 vsri.64 q1, q2, 27
 vst1.64 \{d1,d2,d3,d4\}, [r0]!
 vst2.16 \{d0,d1\}, [r1], r2
 vst3.8 \{d0,d1,d2\}, [r1]!
 vst4.32 \{d6,d7,d8,d9\}, [r7], r4
 vstmia sp!, \{s0-s7\}
 vstmdb sp!, \{d0-d7\}
 vstr.32 s1, [r7]
 vstr.64 d1, [r7, 128]
 vsub.f64 d1, d2, d3
 vsubhn.i32 d1, q2, q3
 vsubl.s32 q1, d2, d3
 vsubw.u32 q1, q2, d3
 vswp d1, d2
 vtrn.32 d1, d2
 vtst.32 d1, d2
 vuzp.8 d1, d2
 vzip.16 q1, q2
}    
Post 30 Sep 2013, 14:54
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revolution
When all else fails, read the source


Joined: 24 Aug 2004
Posts: 16632
Location: In your JS exploiting you and your system
uart777: I am curious to know if you intend to support Thumb, and if so then do you have any ideas about how to detect Thumb/ARM code and/or transitions into and out of Thumb/ARM?

Moved to "Non-x86 architectures" since this appears to be specific for ARM.
Post 01 Oct 2013, 21:15
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