In regards to the atom statements, last time i checked the z2560 set an alltime record in energyefficencie and keeping heat down and the next gen seems to extend the tab. Source http://www.tomshardware.com/reviews/atom-z2760-power-consumption-arm,3387.html
I can remeber back in PDA days where ARM lost most effiencie benchmarks against MIPS, so energy effiences can vary also between RISC cpus. In my opinion its more the core design that influences energy saving (thats way qualcomm has their own arm cores)
Seeing that bench it could be true that A15 outperforms the atom 5x but needs 5x more energy than the atom
Joined: 24 Aug 2004
Location: The total perspective vortex
Indeed there is always a trade-off. Energy usage goes up exponentially with performance. So if you up-clock the Atom at 5x the speed to match the Nexus performance then the energy usage goes up proportional to the square. Alternatively, if you down-clock the Nexus to match the Atom's performance then the energy usage goes down proportional to the inverse square. You can't have your cake and eat too.
Energy usage goes up exponentially with performance. So if you up-clock the Atom at 5x the speed to match the Nexus performance then the energy usage goes up proportional to the square.
Ive always thought there is a sweet spot where effiency and clockspeed match the best. You also cant clock down the ALU infinite (at some freq the ALU can be twice as fast as the cpu clock) there has to be a ratio between clock speed and ALU speed to get the best results. It would be cool if you could post me some lecture about that, in regards about overclocking thats the case to get 1/3 clock speed youll need 3x times the voltage. Why i think the Cortex wouldnt match the energy effiencie is because of the minimum Powerdraw
the cortex has nearly 10x the powerdraw of the atom, while neon and krait cores still have nearly 2x the energy drawn of the atom , and the apq is a dualcore while the atom is quad and at the max powerdrawn their neck to neck
i cant really see the claim that arm is energy effience cause its RISC.
Infact ARM is probably one of the most energy consuming RISC architectures
Some comparison with MIPS source http://www.mips.com/products/cores/32-64-bit-cores/mips32-1074k/#specifications
Base Core: 1074Kf (with FPU)
Configuration: dual core
Process: 40nm G (TSMC)
Libraries: TSMC 12 track, MVt/OD
Frequency: >1.2 Ghz, 1.5 GHz
Coremark/MHz (per core) 2.55
DMIPS/MHz (per core) 2.03
Power: 0.36 mW/Mhz, 0.43 mW/MHz
Area: 4.1 mm2
Cortex A9 Dual Core Hard Macro Implementation (source http://www.arm.com/products/processors/cortex-a/cortex-a9.php)
Process: 40nm G (TSMC)
Frequency: 2000 Mhz (performance optimized),800Mhz (power optimized),
Performance (total DMIPS) : 10,000, 4000
Energy efficiency (DMIPS/Mw): 5.26, 8.0
Total power at target frequency: 1.9W, .5W
so the MIPS outperformsthe ARM in energy effiency by 80 percent, and the atom the arm about 10x even at the energy optimized stage! To keep things short the instruction set does not have a primary impact on powersaving/performance its the parts (core) that the cpu is build of that influences powersaving/performance.
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