;32 bits regs
R001 equ eax
R002 equ edx
R003 equ ecx
R004 equ ebx
R005 equ esi
R006 equ edi
R007 equ ebp
R008 equ r8
R009 equ r9
R010 equ r10
R011 equ r11
R012 equ r12
R013 equ r13
R014 equ r14
R015 equ r15

R200 = 1	;debug infa

R2001 equ R010
R2002 equ R011
R2003 equ R012



