;32 bits regs
R001 equ eax
R002 equ edx
R003 equ ecx
R004 equ ebx
R005 equ esi
R006 equ edi
R007 equ ebp
R008 equ eax
R009 equ edx
R010 equ ecx
R011 equ ebx
R012 equ esi
R013 equ edi
R014 equ ebp
R015 equ eax
R200 = 1	;debug infa

R2001 equ R010
R2002 equ R011
R2003 equ R012